mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-11-27 12:33:00 +00:00
22b2cb39af
* Turn `MemoryOperand` into a struct
* Remove `IntrinsicOperation`
* Remove `PhiNode`
* Remove `Node`
* Turn `Operand` into a struct
* Turn `Operation` into a struct
* Clean up pool management methods
* Add `Arena` allocator
* Move `OperationHelper` to `Operation.Factory`
* Move `OperandHelper` to `Operand.Factory`
* Optimize `Operation` a bit
* Fix `Arena` initialization
* Rename `NativeList<T>` to `ArenaList<T>`
* Reduce `Operand` size from 88 to 56 bytes
* Reduce `Operation` size from 56 to 40 bytes
* Add optimistic interning of Register & Constant operands
* Optimize `RegisterUsage` pass a bit
* Optimize `RemoveUnusedNodes` pass a bit
Iterating in reverse-order allows killing dependency chains in a single
pass.
* Fix PPTC symbols
* Optimize `BasicBlock` a bit
Reduce allocations from `_successor` & `DominanceFrontiers`
* Fix `Operation` resize
* Make `Arena` expandable
Change the arena allocator to be expandable by allocating in pages, with
some of them being pooled. Currently 32 pages are pooled. An LRU removal
mechanism should probably be added to it.
Apparently MHR can allocate bitmaps large enough to exceed the 16MB
limit for the type.
* Move `Arena` & `ArenaList` to `Common`
* Remove `ThreadStaticPool` & co
* Add `PhiOperation`
* Reduce `Operand` size from 56 from 48 bytes
* Add linear-probing to `Operand` intern table
* Optimize `HybridAllocator` a bit
* Add `Allocators` class
* Tune `ArenaAllocator` sizes
* Add page removal mechanism to `ArenaAllocator`
Remove pages which have not been used for more than 5s after each reset.
I am on fence if this would be better using a Gen2 callback object like
the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right
now if a large translation happens, the pages will be freed only after a
reset. This reset may not happen for a while because no new translation
is hit, but the arena base sizes are rather small.
* Fix `OOM` when allocating larger than page size in `ArenaAllocator`
Tweak resizing mechanism for Operand.Uses and Assignemnts.
* Optimize `Optimizer` a bit
* Optimize `Operand.Add<T>/Remove<T>` a bit
* Clean up `PreAllocator`
* Fix phi insertion order
Reduce codegen diffs.
* Fix code alignment
* Use new heuristics for degree of parallelism
* Suppress warnings
* Address gdkchan's feedback
Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that
`Operand.Value` should usually not be modified directly.
* Add fast path to `ArenaAllocator`
* Assembly for `ArenaAllocator.Allocate(ulong)`:
.L0:
mov rax, [rcx+0x18]
lea r8, [rax+rdx]
cmp r8, [rcx+0x10]
ja short .L2
.L1:
mov rdx, [rcx+8]
add rax, [rdx+8]
mov [rcx+0x18], r8
ret
.L2:
jmp ArenaAllocator.AllocateSlow(UInt64)
A few variable/field had to be changed to ulong so that RyuJIT avoids
emitting zero-extends.
* Implement a new heuristic to free pooled pages.
If an arena is used often, it is more likely that its pages will be
needed, so the pages are kept for longer (e.g: during PPTC rebuild or
burst sof compilations). If is not used often, then it is more likely
that its pages will not be needed (e.g: after PPTC rebuild or bursts
of compilations).
* Address riperiperi's feedback
* Use `EqualityComparer<T>` in `IntrusiveList<T>`
Avoids a potential GC hole in `Equals(T, T)`.
608 lines
22 KiB
C#
608 lines
22 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Memory;
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using ARMeilleure.Translation;
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using ARMeilleure.Translation.PTC;
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using System;
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using System.Reflection;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitMemoryHelper
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{
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private const int PageBits = 12;
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private const int PageMask = (1 << PageBits) - 1;
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private enum Extension
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{
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Zx,
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Sx32,
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Sx64
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}
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public static void EmitLoadZx(ArmEmitterContext context, Operand address, int rt, int size)
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{
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EmitLoad(context, address, Extension.Zx, rt, size);
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}
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public static void EmitLoadSx32(ArmEmitterContext context, Operand address, int rt, int size)
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{
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EmitLoad(context, address, Extension.Sx32, rt, size);
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}
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public static void EmitLoadSx64(ArmEmitterContext context, Operand address, int rt, int size)
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{
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EmitLoad(context, address, Extension.Sx64, rt, size);
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}
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private static void EmitLoad(ArmEmitterContext context, Operand address, Extension ext, int rt, int size)
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{
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bool isSimd = IsSimd(context);
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if ((uint)size > (isSimd ? 4 : 3))
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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if (isSimd)
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{
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EmitReadVector(context, address, context.VectorZero(), rt, 0, size);
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}
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else
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{
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EmitReadInt(context, address, rt, size);
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}
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if (!isSimd && !(context.CurrOp is OpCode32 && rt == State.RegisterAlias.Aarch32Pc))
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{
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Operand value = GetInt(context, rt);
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if (ext == Extension.Sx32 || ext == Extension.Sx64)
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{
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OperandType destType = ext == Extension.Sx64 ? OperandType.I64 : OperandType.I32;
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switch (size)
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{
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case 0: value = context.SignExtend8 (destType, value); break;
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case 1: value = context.SignExtend16(destType, value); break;
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case 2: value = context.SignExtend32(destType, value); break;
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}
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}
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SetInt(context, rt, value);
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}
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}
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public static void EmitLoadSimd(
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ArmEmitterContext context,
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Operand address,
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Operand vector,
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int rt,
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int elem,
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int size)
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{
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EmitReadVector(context, address, vector, rt, elem, size);
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}
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public static void EmitStore(ArmEmitterContext context, Operand address, int rt, int size)
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{
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bool isSimd = IsSimd(context);
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if ((uint)size > (isSimd ? 4 : 3))
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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if (isSimd)
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{
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EmitWriteVector(context, address, rt, 0, size);
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}
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else
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{
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EmitWriteInt(context, address, rt, size);
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}
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}
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public static void EmitStoreSimd(
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ArmEmitterContext context,
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Operand address,
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int rt,
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int elem,
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int size)
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{
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EmitWriteVector(context, address, rt, elem, size);
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}
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private static bool IsSimd(ArmEmitterContext context)
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{
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return context.CurrOp is IOpCodeSimd &&
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!(context.CurrOp is OpCodeSimdMemMs ||
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context.CurrOp is OpCodeSimdMemSs);
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}
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private static void EmitReadInt(ArmEmitterContext context, Operand address, int rt, int size)
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{
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size);
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Operand value = default;
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switch (size)
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{
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case 0: value = context.Load8 (physAddr); break;
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case 1: value = context.Load16(physAddr); break;
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case 2: value = context.Load (OperandType.I32, physAddr); break;
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case 3: value = context.Load (OperandType.I64, physAddr); break;
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}
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SetInt(context, rt, value);
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if (!context.Memory.Type.IsHostMapped())
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{
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context.Branch(lblEnd);
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context.MarkLabel(lblSlowPath, BasicBlockFrequency.Cold);
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EmitReadIntFallback(context, address, rt, size);
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context.MarkLabel(lblEnd);
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}
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}
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public static Operand EmitReadIntAligned(ArmEmitterContext context, Operand address, int size)
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{
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if ((uint)size > 4)
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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Operand physAddr = EmitPtPointerLoad(context, address, default, write: false, size);
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return size switch
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{
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0 => context.Load8(physAddr),
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1 => context.Load16(physAddr),
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2 => context.Load(OperandType.I32, physAddr),
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3 => context.Load(OperandType.I64, physAddr),
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_ => context.Load(OperandType.V128, physAddr)
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};
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}
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private static void EmitReadVector(
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ArmEmitterContext context,
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Operand address,
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Operand vector,
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int rt,
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int elem,
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int size)
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{
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size);
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Operand value = default;
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switch (size)
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{
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case 0: value = context.VectorInsert8 (vector, context.Load8(physAddr), elem); break;
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case 1: value = context.VectorInsert16(vector, context.Load16(physAddr), elem); break;
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case 2: value = context.VectorInsert (vector, context.Load(OperandType.I32, physAddr), elem); break;
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case 3: value = context.VectorInsert (vector, context.Load(OperandType.I64, physAddr), elem); break;
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case 4: value = context.Load (OperandType.V128, physAddr); break;
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}
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context.Copy(GetVec(rt), value);
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if (!context.Memory.Type.IsHostMapped())
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{
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context.Branch(lblEnd);
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context.MarkLabel(lblSlowPath, BasicBlockFrequency.Cold);
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EmitReadVectorFallback(context, address, vector, rt, elem, size);
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context.MarkLabel(lblEnd);
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}
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}
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private static Operand VectorCreate(ArmEmitterContext context, Operand value)
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{
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return context.VectorInsert(context.VectorZero(), value, 0);
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}
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private static void EmitWriteInt(ArmEmitterContext context, Operand address, int rt, int size)
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{
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true, size);
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Operand value = GetInt(context, rt);
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if (size < 3 && value.Type == OperandType.I64)
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{
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value = context.ConvertI64ToI32(value);
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}
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switch (size)
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{
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case 0: context.Store8 (physAddr, value); break;
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case 1: context.Store16(physAddr, value); break;
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case 2: context.Store (physAddr, value); break;
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case 3: context.Store (physAddr, value); break;
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}
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if (!context.Memory.Type.IsHostMapped())
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{
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context.Branch(lblEnd);
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context.MarkLabel(lblSlowPath, BasicBlockFrequency.Cold);
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EmitWriteIntFallback(context, address, rt, size);
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context.MarkLabel(lblEnd);
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}
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}
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public static void EmitWriteIntAligned(ArmEmitterContext context, Operand address, Operand value, int size)
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{
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if ((uint)size > 4)
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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Operand physAddr = EmitPtPointerLoad(context, address, default, write: true, size);
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if (size < 3 && value.Type == OperandType.I64)
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{
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value = context.ConvertI64ToI32(value);
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}
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if (size == 0)
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{
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context.Store8(physAddr, value);
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}
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else if (size == 1)
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{
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context.Store16(physAddr, value);
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}
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else
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{
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context.Store(physAddr, value);
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}
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}
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private static void EmitWriteVector(
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ArmEmitterContext context,
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Operand address,
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int rt,
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int elem,
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int size)
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{
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true, size);
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Operand value = GetVec(rt);
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switch (size)
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{
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case 0: context.Store8 (physAddr, context.VectorExtract8(value, elem)); break;
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case 1: context.Store16(physAddr, context.VectorExtract16(value, elem)); break;
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case 2: context.Store (physAddr, context.VectorExtract(OperandType.I32, value, elem)); break;
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case 3: context.Store (physAddr, context.VectorExtract(OperandType.I64, value, elem)); break;
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case 4: context.Store (physAddr, value); break;
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}
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if (!context.Memory.Type.IsHostMapped())
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{
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context.Branch(lblEnd);
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context.MarkLabel(lblSlowPath, BasicBlockFrequency.Cold);
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EmitWriteVectorFallback(context, address, rt, elem, size);
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context.MarkLabel(lblEnd);
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}
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}
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public static Operand EmitPtPointerLoad(ArmEmitterContext context, Operand address, Operand lblSlowPath, bool write, int size)
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{
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if (context.Memory.Type.IsHostMapped())
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{
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return EmitHostMappedPointer(context, address);
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}
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int ptLevelBits = context.Memory.AddressSpaceBits - PageBits;
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int ptLevelSize = 1 << ptLevelBits;
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int ptLevelMask = ptLevelSize - 1;
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Operand addrRotated = size != 0 ? context.RotateRight(address, Const(size)) : address;
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Operand addrShifted = context.ShiftRightUI(addrRotated, Const(PageBits - size));
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Operand pte = !context.HasPtc
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? Const(context.Memory.PageTablePointer.ToInt64())
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: Const(context.Memory.PageTablePointer.ToInt64(), Ptc.PageTableSymbol);
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Operand pteOffset = context.BitwiseAnd(addrShifted, Const(addrShifted.Type, ptLevelMask));
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if (pteOffset.Type == OperandType.I32)
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{
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pteOffset = context.ZeroExtend32(OperandType.I64, pteOffset);
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}
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pte = context.Load(OperandType.I64, context.Add(pte, context.ShiftLeft(pteOffset, Const(3))));
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if (addrShifted.Type == OperandType.I32)
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{
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addrShifted = context.ZeroExtend32(OperandType.I64, addrShifted);
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}
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// If the VA is out of range, or not aligned to the access size, force PTE to 0 by masking it.
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pte = context.BitwiseAnd(pte, context.ShiftRightSI(context.Add(addrShifted, Const(-(long)ptLevelSize)), Const(63)));
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if (lblSlowPath != default)
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{
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if (write)
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{
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context.BranchIf(lblSlowPath, pte, Const(0L), Comparison.LessOrEqual);
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pte = context.BitwiseAnd(pte, Const(0xffffffffffffUL)); // Ignore any software protection bits. (they are still used by C# memory access)
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}
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else
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{
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pte = context.ShiftLeft(pte, Const(1));
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context.BranchIf(lblSlowPath, pte, Const(0L), Comparison.LessOrEqual);
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pte = context.ShiftRightUI(pte, Const(1));
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}
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}
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else
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{
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// When no label is provided to jump to a slow path if the address is invalid,
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// we do the validation ourselves, and throw if needed.
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Operand lblNotWatched = Label();
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// Is the page currently being tracked for read/write? If so we need to call SignalMemoryTracking.
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context.BranchIf(lblNotWatched, pte, Const(0L), Comparison.GreaterOrEqual, BasicBlockFrequency.Cold);
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// Signal memory tracking. Size here doesn't matter as address is assumed to be size aligned here.
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SignalMemoryTracking)), address, Const(1UL), Const(write ? 1 : 0));
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context.MarkLabel(lblNotWatched);
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pte = context.BitwiseAnd(pte, Const(0xffffffffffffUL)); // Ignore any software protection bits. (they are still used by C# memory access)
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Operand lblNonNull = Label();
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// Skip exception if the PTE address is non-null (not zero).
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context.BranchIfTrue(lblNonNull, pte, BasicBlockFrequency.Cold);
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// The call is not expected to return (it should throw).
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
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context.MarkLabel(lblNonNull);
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}
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Operand pageOffset = context.BitwiseAnd(address, Const(address.Type, PageMask));
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if (pageOffset.Type == OperandType.I32)
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{
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pageOffset = context.ZeroExtend32(OperandType.I64, pageOffset);
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}
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return context.Add(pte, pageOffset);
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}
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public static Operand EmitHostMappedPointer(ArmEmitterContext context, Operand address)
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{
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if (address.Type == OperandType.I32)
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{
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address = context.ZeroExtend32(OperandType.I64, address);
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}
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if (context.Memory.Type == MemoryManagerType.HostMapped)
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{
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Operand mask = Const(ulong.MaxValue >> (64 - context.Memory.AddressSpaceBits));
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address = context.BitwiseAnd(address, mask);
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}
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Operand baseAddr = !context.HasPtc
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? Const(context.Memory.PageTablePointer.ToInt64())
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: Const(context.Memory.PageTablePointer.ToInt64(), Ptc.PageTableSymbol);
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return context.Add(baseAddr, address);
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}
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private static void EmitReadIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
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{
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MethodInfo info = null;
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switch (size)
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{
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case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); break;
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case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); break;
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case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); break;
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case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break;
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}
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SetInt(context, rt, context.Call(info, address));
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}
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private static void EmitReadVectorFallback(
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ArmEmitterContext context,
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Operand address,
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Operand vector,
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int rt,
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int elem,
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int size)
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{
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MethodInfo info = null;
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switch (size)
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{
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case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); break;
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case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); break;
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case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); break;
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case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break;
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case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadVector128)); break;
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}
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Operand value = context.Call(info, address);
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|
|
|
switch (size)
|
|
{
|
|
case 0: value = context.VectorInsert8 (vector, value, elem); break;
|
|
case 1: value = context.VectorInsert16(vector, value, elem); break;
|
|
case 2: value = context.VectorInsert (vector, value, elem); break;
|
|
case 3: value = context.VectorInsert (vector, value, elem); break;
|
|
}
|
|
|
|
context.Copy(GetVec(rt), value);
|
|
}
|
|
|
|
private static void EmitWriteIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
|
|
{
|
|
MethodInfo info = null;
|
|
|
|
switch (size)
|
|
{
|
|
case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); break;
|
|
case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); break;
|
|
case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); break;
|
|
case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); break;
|
|
}
|
|
|
|
Operand value = GetInt(context, rt);
|
|
|
|
if (size < 3 && value.Type == OperandType.I64)
|
|
{
|
|
value = context.ConvertI64ToI32(value);
|
|
}
|
|
|
|
context.Call(info, address, value);
|
|
}
|
|
|
|
private static void EmitWriteVectorFallback(
|
|
ArmEmitterContext context,
|
|
Operand address,
|
|
int rt,
|
|
int elem,
|
|
int size)
|
|
{
|
|
MethodInfo info = null;
|
|
|
|
switch (size)
|
|
{
|
|
case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); break;
|
|
case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); break;
|
|
case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); break;
|
|
case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); break;
|
|
case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128)); break;
|
|
}
|
|
|
|
Operand value = default;
|
|
|
|
if (size < 4)
|
|
{
|
|
switch (size)
|
|
{
|
|
case 0: value = context.VectorExtract8 (GetVec(rt), elem); break;
|
|
case 1: value = context.VectorExtract16(GetVec(rt), elem); break;
|
|
case 2: value = context.VectorExtract (OperandType.I32, GetVec(rt), elem); break;
|
|
case 3: value = context.VectorExtract (OperandType.I64, GetVec(rt), elem); break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
value = GetVec(rt);
|
|
}
|
|
|
|
context.Call(info, address, value);
|
|
}
|
|
|
|
private static Operand GetInt(ArmEmitterContext context, int rt)
|
|
{
|
|
return context.CurrOp is OpCode32 ? GetIntA32(context, rt) : GetIntOrZR(context, rt);
|
|
}
|
|
|
|
private static void SetInt(ArmEmitterContext context, int rt, Operand value)
|
|
{
|
|
if (context.CurrOp is OpCode32)
|
|
{
|
|
SetIntA32(context, rt, value);
|
|
}
|
|
else
|
|
{
|
|
SetIntOrZR(context, rt, value);
|
|
}
|
|
}
|
|
|
|
// ARM32 helpers.
|
|
public static Operand GetMemM(ArmEmitterContext context, bool setCarry = true)
|
|
{
|
|
switch (context.CurrOp)
|
|
{
|
|
case OpCode32MemRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
|
|
|
|
case OpCode32MemReg op: return GetIntA32(context, op.Rm);
|
|
|
|
case OpCode32Mem op: return Const(op.Immediate);
|
|
|
|
case OpCode32SimdMemImm op: return Const(op.Immediate);
|
|
|
|
default: throw InvalidOpCodeType(context.CurrOp);
|
|
}
|
|
}
|
|
|
|
private static Exception InvalidOpCodeType(OpCode opCode)
|
|
{
|
|
return new InvalidOperationException($"Invalid OpCode type \"{opCode?.GetType().Name ?? "null"}\".");
|
|
}
|
|
|
|
public static Operand GetMShiftedByImmediate(ArmEmitterContext context, OpCode32MemRsImm op, bool setCarry)
|
|
{
|
|
Operand m = GetIntA32(context, op.Rm);
|
|
|
|
int shift = op.Immediate;
|
|
|
|
if (shift == 0)
|
|
{
|
|
switch (op.ShiftType)
|
|
{
|
|
case ShiftType.Lsr: shift = 32; break;
|
|
case ShiftType.Asr: shift = 32; break;
|
|
case ShiftType.Ror: shift = 1; break;
|
|
}
|
|
}
|
|
|
|
if (shift != 0)
|
|
{
|
|
setCarry &= false;
|
|
|
|
switch (op.ShiftType)
|
|
{
|
|
case ShiftType.Lsl: m = InstEmitAluHelper.GetLslC(context, m, setCarry, shift); break;
|
|
case ShiftType.Lsr: m = InstEmitAluHelper.GetLsrC(context, m, setCarry, shift); break;
|
|
case ShiftType.Asr: m = InstEmitAluHelper.GetAsrC(context, m, setCarry, shift); break;
|
|
case ShiftType.Ror:
|
|
if (op.Immediate != 0)
|
|
{
|
|
m = InstEmitAluHelper.GetRorC(context, m, setCarry, shift);
|
|
}
|
|
else
|
|
{
|
|
m = InstEmitAluHelper.GetRrxC(context, m, setCarry);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
return m;
|
|
}
|
|
}
|
|
}
|