mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-05 08:17:25 +00:00
514218ab98
* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions * Address PR feedback * Address PR feedback * Remove another useless temp var * nit: Alignment * Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount() * Fix encodings and move flag bit test out of the loop
185 lines
No EOL
5.1 KiB
C#
185 lines
No EOL
5.1 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using static ChocolArm64.Instruction.AInstEmitMemoryHelper;
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using static ChocolArm64.Instruction.AInstEmitSimdHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Ld__Vms(AILEmitterCtx Context)
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{
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EmitSimdMemMs(Context, IsLoad: true);
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}
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public static void Ld__Vss(AILEmitterCtx Context)
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{
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EmitSimdMemSs(Context, IsLoad: true);
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}
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public static void St__Vms(AILEmitterCtx Context)
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{
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EmitSimdMemMs(Context, IsLoad: false);
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}
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public static void St__Vss(AILEmitterCtx Context)
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{
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EmitSimdMemSs(Context, IsLoad: false);
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}
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private static void EmitSimdMemMs(AILEmitterCtx Context, bool IsLoad)
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{
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AOpCodeSimdMemMs Op = (AOpCodeSimdMemMs)Context.CurrOp;
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int Offset = 0;
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for (int Rep = 0; Rep < Op.Reps; Rep++)
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for (int Elem = 0; Elem < Op.Elems; Elem++)
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for (int SElem = 0; SElem < Op.SElems; SElem++)
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{
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int Rtt = (Op.Rt + Rep + SElem) & 0x1f;
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if (IsLoad)
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{
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdint(Op.Rn);
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Context.EmitLdc_I8(Offset);
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Context.Emit(OpCodes.Add);
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EmitReadZxCall(Context, Op.Size);
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EmitVectorInsert(Context, Rtt, Elem, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64 && Elem == Op.Elems - 1)
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{
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EmitVectorZeroUpper(Context, Rtt);
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}
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}
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else
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{
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdint(Op.Rn);
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Context.EmitLdc_I8(Offset);
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Context.Emit(OpCodes.Add);
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EmitVectorExtractZx(Context, Rtt, Elem, Op.Size);
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EmitWriteCall(Context, Op.Size);
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}
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Offset += 1 << Op.Size;
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}
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if (Op.WBack)
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{
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EmitSimdMemWBack(Context, Offset);
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}
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}
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private static void EmitSimdMemSs(AILEmitterCtx Context, bool IsLoad)
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{
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AOpCodeSimdMemSs Op = (AOpCodeSimdMemSs)Context.CurrOp;
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int Offset = 0;
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void EmitMemAddress()
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{
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdint(Op.Rn);
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Context.EmitLdc_I8(Offset);
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Context.Emit(OpCodes.Add);
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}
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if (Op.Replicate)
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{
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//Only loads uses the replicate mode.
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if (!IsLoad)
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{
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throw new InvalidOperationException();
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}
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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for (int SElem = 0; SElem < Op.SElems; SElem++)
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{
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int Rt = (Op.Rt + SElem) & 0x1f;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitMemAddress();
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EmitReadZxCall(Context, Op.Size);
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EmitVectorInsert(Context, Rt, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Rt);
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}
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Offset += 1 << Op.Size;
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}
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}
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else
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{
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for (int SElem = 0; SElem < Op.SElems; SElem++)
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{
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int Rt = (Op.Rt + SElem) & 0x1f;
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if (IsLoad)
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{
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EmitMemAddress();
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EmitReadZxCall(Context, Op.Size);
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EmitVectorInsert(Context, Rt, Op.Index, Op.Size);
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}
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else
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{
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EmitMemAddress();
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EmitVectorExtractZx(Context, Rt, Op.Index, Op.Size);
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EmitWriteCall(Context, Op.Size);
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}
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Offset += 1 << Op.Size;
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}
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}
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if (Op.WBack)
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{
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EmitSimdMemWBack(Context, Offset);
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}
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}
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private static void EmitSimdMemWBack(AILEmitterCtx Context, int Offset)
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{
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AOpCodeMemReg Op = (AOpCodeMemReg)Context.CurrOp;
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Context.EmitLdint(Op.Rn);
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if (Op.Rm != AThreadState.ZRIndex)
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{
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Context.EmitLdint(Op.Rm);
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}
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else
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{
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Context.EmitLdc_I8(Offset);
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}
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Context.Emit(OpCodes.Add);
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Context.EmitStint(Op.Rn);
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}
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}
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} |