mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-05 00:07:25 +00:00
d4187aaa9d
* (Re)Implement format reinterpretation, other changes * Implement writeback to guest memory, some refactoring * More refactoring, implement reinterpretation the old way again * Clean up * Some fixes on M2MF (old Dma engine), added partial support for P2MF, fix conditional ssy, add Z24S8 zeta format, other fixes * nit: Formatting * Address PR feedback
292 lines
No EOL
8.8 KiB
C#
292 lines
No EOL
8.8 KiB
C#
using System;
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using static Ryujinx.Graphics.Gal.Shader.ShaderDecodeHelper;
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namespace Ryujinx.Graphics.Gal.Shader
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{
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static partial class ShaderDecode
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{
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private const int TempRegStart = 0x100;
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private const int ____ = 0x0;
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private const int R___ = 0x1;
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private const int _G__ = 0x2;
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private const int RG__ = 0x3;
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private const int __B_ = 0x4;
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private const int RGB_ = 0x7;
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private const int ___A = 0x8;
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private const int R__A = 0x9;
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private const int _G_A = 0xa;
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private const int RG_A = 0xb;
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private const int __BA = 0xc;
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private const int R_BA = 0xd;
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private const int _GBA = 0xe;
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private const int RGBA = 0xf;
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private static int[,] MaskLut = new int[,]
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{
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{ ____, ____, ____, ____, ____, ____, ____, ____ },
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{ R___, _G__, __B_, ___A, RG__, R__A, _G_A, __BA },
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{ R___, _G__, __B_, ___A, RG__, ____, ____, ____ },
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{ RGB_, RG_A, R_BA, _GBA, RGBA, ____, ____, ____ }
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};
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public static void Ld_A(ShaderIrBlock Block, long OpCode, int Position)
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{
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ShaderIrNode[] Opers = OpCode.Abuf20();
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//Used by GS
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ShaderIrOperGpr Vertex = OpCode.Gpr39();
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int Index = 0;
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foreach (ShaderIrNode OperA in Opers)
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{
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ShaderIrOperGpr OperD = OpCode.Gpr0();
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OperD.Index += Index++;
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperD, OperA)));
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}
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}
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public static void Ld_C(ShaderIrBlock Block, long OpCode, int Position)
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{
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int CbufPos = OpCode.Read(22, 0x3fff);
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int CbufIndex = OpCode.Read(36, 0x1f);
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int Type = OpCode.Read(48, 7);
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if (Type > 5)
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{
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throw new InvalidOperationException();
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}
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ShaderIrOperGpr Temp = ShaderIrOperGpr.MakeTemporary();
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Block.AddNode(new ShaderIrAsg(Temp, OpCode.Gpr8()));
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int Count = Type == 5 ? 2 : 1;
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for (int Index = 0; Index < Count; Index++)
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{
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ShaderIrOperCbuf OperA = new ShaderIrOperCbuf(CbufIndex, CbufPos, Temp);
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ShaderIrOperGpr OperD = OpCode.Gpr0();
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OperA.Pos += Index;
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OperD.Index += Index;
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if (!OperD.IsValidRegister)
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{
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break;
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}
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ShaderIrNode Node = OperA;
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if (Type < 4)
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{
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//This is a 8 or 16 bits type.
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bool Signed = (Type & 1) != 0;
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int Size = 8 << (Type >> 1);
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Node = ExtendTo32(Node, Signed, Size);
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}
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperD, Node)));
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}
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}
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public static void St_A(ShaderIrBlock Block, long OpCode, int Position)
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{
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ShaderIrNode[] Opers = OpCode.Abuf20();
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int Index = 0;
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foreach (ShaderIrNode OperA in Opers)
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{
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ShaderIrOperGpr OperD = OpCode.Gpr0();
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OperD.Index += Index++;
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperA, OperD)));
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}
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}
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public static void Texq(ShaderIrBlock Block, long OpCode, int Position)
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{
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ShaderIrNode OperD = OpCode.Gpr0();
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ShaderIrNode OperA = OpCode.Gpr8();
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ShaderTexqInfo Info = (ShaderTexqInfo)(OpCode.Read(22, 0x1f));
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ShaderIrMetaTexq Meta0 = new ShaderIrMetaTexq(Info, 0);
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ShaderIrMetaTexq Meta1 = new ShaderIrMetaTexq(Info, 1);
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ShaderIrNode OperC = OpCode.Imm13_36();
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ShaderIrOp Op0 = new ShaderIrOp(ShaderIrInst.Texq, OperA, null, OperC, Meta0);
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ShaderIrOp Op1 = new ShaderIrOp(ShaderIrInst.Texq, OperA, null, OperC, Meta1);
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperD, Op0)));
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperA, Op1))); //Is this right?
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}
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public static void Tex(ShaderIrBlock Block, long OpCode, int Position)
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{
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EmitTex(Block, OpCode, GprHandle: false);
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}
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public static void Tex_B(ShaderIrBlock Block, long OpCode, int Position)
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{
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EmitTex(Block, OpCode, GprHandle: true);
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}
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private static void EmitTex(ShaderIrBlock Block, long OpCode, bool GprHandle)
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{
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//TODO: Support other formats.
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ShaderIrOperGpr[] Coords = new ShaderIrOperGpr[2];
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for (int Index = 0; Index < Coords.Length; Index++)
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{
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Coords[Index] = OpCode.Gpr8();
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Coords[Index].Index += Index;
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if (Coords[Index].Index > ShaderIrOperGpr.ZRIndex)
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{
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Coords[Index].Index = ShaderIrOperGpr.ZRIndex;
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}
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}
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int ChMask = OpCode.Read(31, 0xf);
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ShaderIrNode OperC = GprHandle
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? (ShaderIrNode)OpCode.Gpr20()
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: (ShaderIrNode)OpCode.Imm13_36();
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ShaderIrInst Inst = GprHandle ? ShaderIrInst.Texb : ShaderIrInst.Texs;
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for (int Ch = 0; Ch < 4; Ch++)
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{
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ShaderIrOperGpr Dst = new ShaderIrOperGpr(TempRegStart + Ch);
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ShaderIrMetaTex Meta = new ShaderIrMetaTex(Ch);
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ShaderIrOp Op = new ShaderIrOp(Inst, Coords[0], Coords[1], OperC, Meta);
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Op)));
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}
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int RegInc = 0;
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for (int Ch = 0; Ch < 4; Ch++)
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{
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if (!IsChannelUsed(ChMask, Ch))
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{
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continue;
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}
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ShaderIrOperGpr Src = new ShaderIrOperGpr(TempRegStart + Ch);
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ShaderIrOperGpr Dst = OpCode.Gpr0();
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Dst.Index += RegInc++;
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if (Dst.Index >= ShaderIrOperGpr.ZRIndex)
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{
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continue;
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}
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Src)));
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}
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}
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public static void Texs(ShaderIrBlock Block, long OpCode, int Position)
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{
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EmitTexs(Block, OpCode, ShaderIrInst.Texs);
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}
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public static void Tlds(ShaderIrBlock Block, long OpCode, int Position)
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{
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EmitTexs(Block, OpCode, ShaderIrInst.Txlf);
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}
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private static void EmitTexs(ShaderIrBlock Block, long OpCode, ShaderIrInst Inst)
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{
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//TODO: Support other formats.
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ShaderIrNode OperA = OpCode.Gpr8();
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ShaderIrNode OperB = OpCode.Gpr20();
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ShaderIrNode OperC = OpCode.Imm13_36();
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int LutIndex;
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LutIndex = OpCode.Gpr0 ().Index != ShaderIrOperGpr.ZRIndex ? 1 : 0;
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LutIndex |= OpCode.Gpr28().Index != ShaderIrOperGpr.ZRIndex ? 2 : 0;
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if (LutIndex == 0)
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{
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//Both registers are RZ, color is not written anywhere.
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//So, the intruction is basically a no-op.
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return;
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}
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int ChMask = MaskLut[LutIndex, OpCode.Read(50, 7)];
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for (int Ch = 0; Ch < 4; Ch++)
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{
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ShaderIrOperGpr Dst = new ShaderIrOperGpr(TempRegStart + Ch);
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ShaderIrMetaTex Meta = new ShaderIrMetaTex(Ch);
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ShaderIrOp Op = new ShaderIrOp(Inst, OperA, OperB, OperC, Meta);
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Op)));
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}
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int RegInc = 0;
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ShaderIrOperGpr GetDst()
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{
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ShaderIrOperGpr Dst;
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switch (LutIndex)
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{
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case 1: Dst = OpCode.Gpr0(); break;
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case 2: Dst = OpCode.Gpr28(); break;
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case 3: Dst = (RegInc >> 1) != 0
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? OpCode.Gpr28()
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: OpCode.Gpr0 (); break;
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default: throw new InvalidOperationException();
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}
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Dst.Index += RegInc++ & 1;
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return Dst;
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}
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for (int Ch = 0; Ch < 4; Ch++)
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{
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if (!IsChannelUsed(ChMask, Ch))
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{
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continue;
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}
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ShaderIrOperGpr Src = new ShaderIrOperGpr(TempRegStart + Ch);
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ShaderIrOperGpr Dst = GetDst();
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if (Dst.Index != ShaderIrOperGpr.ZRIndex)
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{
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Src)));
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}
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}
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}
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private static bool IsChannelUsed(int ChMask, int Ch)
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{
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return (ChMask & (1 << Ch)) != 0;
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}
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}
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} |