mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-11-27 04:23:01 +00:00
22b2cb39af
* Turn `MemoryOperand` into a struct
* Remove `IntrinsicOperation`
* Remove `PhiNode`
* Remove `Node`
* Turn `Operand` into a struct
* Turn `Operation` into a struct
* Clean up pool management methods
* Add `Arena` allocator
* Move `OperationHelper` to `Operation.Factory`
* Move `OperandHelper` to `Operand.Factory`
* Optimize `Operation` a bit
* Fix `Arena` initialization
* Rename `NativeList<T>` to `ArenaList<T>`
* Reduce `Operand` size from 88 to 56 bytes
* Reduce `Operation` size from 56 to 40 bytes
* Add optimistic interning of Register & Constant operands
* Optimize `RegisterUsage` pass a bit
* Optimize `RemoveUnusedNodes` pass a bit
Iterating in reverse-order allows killing dependency chains in a single
pass.
* Fix PPTC symbols
* Optimize `BasicBlock` a bit
Reduce allocations from `_successor` & `DominanceFrontiers`
* Fix `Operation` resize
* Make `Arena` expandable
Change the arena allocator to be expandable by allocating in pages, with
some of them being pooled. Currently 32 pages are pooled. An LRU removal
mechanism should probably be added to it.
Apparently MHR can allocate bitmaps large enough to exceed the 16MB
limit for the type.
* Move `Arena` & `ArenaList` to `Common`
* Remove `ThreadStaticPool` & co
* Add `PhiOperation`
* Reduce `Operand` size from 56 from 48 bytes
* Add linear-probing to `Operand` intern table
* Optimize `HybridAllocator` a bit
* Add `Allocators` class
* Tune `ArenaAllocator` sizes
* Add page removal mechanism to `ArenaAllocator`
Remove pages which have not been used for more than 5s after each reset.
I am on fence if this would be better using a Gen2 callback object like
the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right
now if a large translation happens, the pages will be freed only after a
reset. This reset may not happen for a while because no new translation
is hit, but the arena base sizes are rather small.
* Fix `OOM` when allocating larger than page size in `ArenaAllocator`
Tweak resizing mechanism for Operand.Uses and Assignemnts.
* Optimize `Optimizer` a bit
* Optimize `Operand.Add<T>/Remove<T>` a bit
* Clean up `PreAllocator`
* Fix phi insertion order
Reduce codegen diffs.
* Fix code alignment
* Use new heuristics for degree of parallelism
* Suppress warnings
* Address gdkchan's feedback
Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that
`Operand.Value` should usually not be modified directly.
* Add fast path to `ArenaAllocator`
* Assembly for `ArenaAllocator.Allocate(ulong)`:
.L0:
mov rax, [rcx+0x18]
lea r8, [rax+rdx]
cmp r8, [rcx+0x10]
ja short .L2
.L1:
mov rdx, [rcx+8]
add rax, [rdx+8]
mov [rcx+0x18], r8
ret
.L2:
jmp ArenaAllocator.AllocateSlow(UInt64)
A few variable/field had to be changed to ulong so that RyuJIT avoids
emitting zero-extends.
* Implement a new heuristic to free pooled pages.
If an arena is used often, it is more likely that its pages will be
needed, so the pages are kept for longer (e.g: during PPTC rebuild or
burst sof compilations). If is not used often, then it is more likely
that its pages will not be needed (e.g: after PPTC rebuild or bursts
of compilations).
* Address riperiperi's feedback
* Use `EqualityComparer<T>` in `IntrusiveList<T>`
Avoids a potential GC hole in `Equals(T, T)`.
595 lines
23 KiB
C#
595 lines
23 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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#region "Masks"
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// Same as InstEmitSimdMove, as the instructions do the same thing.
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private static readonly long[] _masksE0_Uzp = new long[]
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{
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13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0,
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11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0
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};
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private static readonly long[] _masksE1_Uzp = new long[]
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{
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15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0,
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15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0
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};
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#endregion
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public static void Vmov_I(ArmEmitterContext context)
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{
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EmitVectorImmUnaryOp32(context, (op1) => op1);
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}
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public static void Vmvn_I(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorUnaryOpSimd32(context, (op1) =>
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{
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Operand mask = X86GetAllElements(context, -1L);
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return context.AddIntrinsic(Intrinsic.X86Pandn, op1, mask);
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});
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}
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else
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{
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EmitVectorUnaryOpZx32(context, (op1) => context.BitwiseNot(op1));
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}
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}
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public static void Vmvn_II(ArmEmitterContext context)
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{
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EmitVectorImmUnaryOp32(context, (op1) => context.BitwiseNot(op1));
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}
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public static void Vmov_GS(ArmEmitterContext context)
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{
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OpCode32SimdMovGp op = (OpCode32SimdMovGp)context.CurrOp;
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Operand vec = GetVecA32(op.Vn >> 2);
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if (op.Op == 1)
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{
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// To general purpose.
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Operand value = context.VectorExtract(OperandType.I32, vec, op.Vn & 0x3);
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SetIntA32(context, op.Rt, value);
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}
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else
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{
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// From general purpose.
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Operand value = GetIntA32(context, op.Rt);
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context.Copy(vec, context.VectorInsert(vec, value, op.Vn & 0x3));
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}
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}
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public static void Vmov_G1(ArmEmitterContext context)
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{
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OpCode32SimdMovGpElem op = (OpCode32SimdMovGpElem)context.CurrOp;
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int index = op.Index + ((op.Vd & 1) << (3 - op.Size));
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if (op.Op == 1)
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{
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// To general purpose.
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Operand value = EmitVectorExtract32(context, op.Vd >> 1, index, op.Size, !op.U);
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SetIntA32(context, op.Rt, value);
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}
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else
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{
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// From general purpose.
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Operand vec = GetVecA32(op.Vd >> 1);
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Operand value = GetIntA32(context, op.Rt);
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context.Copy(vec, EmitVectorInsert(context, vec, value, index, op.Size));
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}
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}
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public static void Vmov_G2(ArmEmitterContext context)
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{
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OpCode32SimdMovGpDouble op = (OpCode32SimdMovGpDouble)context.CurrOp;
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Operand vec = GetVecA32(op.Vm >> 2);
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int vm1 = op.Vm + 1;
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bool sameOwnerVec = (op.Vm >> 2) == (vm1 >> 2);
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Operand vec2 = sameOwnerVec ? vec : GetVecA32(vm1 >> 2);
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if (op.Op == 1)
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{
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// To general purpose.
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Operand lowValue = context.VectorExtract(OperandType.I32, vec, op.Vm & 3);
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SetIntA32(context, op.Rt, lowValue);
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Operand highValue = context.VectorExtract(OperandType.I32, vec2, vm1 & 3);
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SetIntA32(context, op.Rt2, highValue);
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}
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else
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{
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// From general purpose.
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Operand lowValue = GetIntA32(context, op.Rt);
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Operand resultVec = context.VectorInsert(vec, lowValue, op.Vm & 3);
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Operand highValue = GetIntA32(context, op.Rt2);
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if (sameOwnerVec)
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{
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context.Copy(vec, context.VectorInsert(resultVec, highValue, vm1 & 3));
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}
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else
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{
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context.Copy(vec, resultVec);
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context.Copy(vec2, context.VectorInsert(vec2, highValue, vm1 & 3));
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}
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}
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}
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public static void Vmov_GD(ArmEmitterContext context)
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{
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OpCode32SimdMovGpDouble op = (OpCode32SimdMovGpDouble)context.CurrOp;
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Operand vec = GetVecA32(op.Vm >> 1);
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if (op.Op == 1)
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{
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// To general purpose.
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Operand value = context.VectorExtract(OperandType.I64, vec, op.Vm & 1);
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SetIntA32(context, op.Rt, context.ConvertI64ToI32(value));
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SetIntA32(context, op.Rt2, context.ConvertI64ToI32(context.ShiftRightUI(value, Const(32))));
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}
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else
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{
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// From general purpose.
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Operand lowValue = GetIntA32(context, op.Rt);
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Operand highValue = GetIntA32(context, op.Rt2);
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Operand value = context.BitwiseOr(
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context.ZeroExtend32(OperandType.I64, lowValue),
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context.ShiftLeft(context.ZeroExtend32(OperandType.I64, highValue), Const(32)));
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context.Copy(vec, context.VectorInsert(vec, value, op.Vm & 1));
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}
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}
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public static void Vmovl(ArmEmitterContext context)
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{
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OpCode32SimdLong op = (OpCode32SimdLong)context.CurrOp;
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Operand res = context.VectorZero();
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, !op.U);
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if (op.Size == 2)
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{
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if (op.U)
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{
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me = context.ZeroExtend32(OperandType.I64, me);
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}
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else
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{
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me = context.SignExtend32(OperandType.I64, me);
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}
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}
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res = EmitVectorInsert(context, res, me, index, op.Size + 1);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Vtbl(ArmEmitterContext context)
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{
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OpCode32SimdTbl op = (OpCode32SimdTbl)context.CurrOp;
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bool extension = op.Opc == 1;
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int length = op.Length + 1;
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if (Optimizations.UseSsse3)
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{
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Operand d = GetVecA32(op.Qd);
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Operand m = EmitMoveDoubleWordToSide(context, GetVecA32(op.Qm), op.Vm, 0);
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Operand res;
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Operand mask = X86GetAllElements(context, 0x0707070707070707L);
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// Fast path for single register table.
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{
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Operand n = EmitMoveDoubleWordToSide(context, GetVecA32(op.Qn), op.Vn, 0);
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Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, mask);
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mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m);
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res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mMask);
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}
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for (int index = 1; index < length; index++)
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{
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int newVn = (op.Vn + index) & 0x1F;
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(int qn, int ind) = GetQuadwordAndSubindex(newVn, op.RegisterSize);
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Operand ni = EmitMoveDoubleWordToSide(context, GetVecA32(qn), newVn, 0);
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Operand idxMask = X86GetAllElements(context, 0x0808080808080808L * index);
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Operand mSubMask = context.AddIntrinsic(Intrinsic.X86Psubb, m, idxMask);
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Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, mSubMask, mask);
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mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, mSubMask);
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Operand res2 = context.AddIntrinsic(Intrinsic.X86Pshufb, ni, mMask);
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res = context.AddIntrinsic(Intrinsic.X86Por, res, res2);
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}
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if (extension)
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{
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Operand idxMask = X86GetAllElements(context, (0x0808080808080808L * length) - 0x0101010101010101L);
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Operand zeroMask = context.VectorZero();
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Operand mPosMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, idxMask);
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Operand mNegMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, zeroMask, m);
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Operand mMask = context.AddIntrinsic(Intrinsic.X86Por, mPosMask, mNegMask);
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Operand dMask = context.AddIntrinsic(Intrinsic.X86Pand, EmitMoveDoubleWordToSide(context, d, op.Vd, 0), mMask);
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res = context.AddIntrinsic(Intrinsic.X86Por, res, dMask);
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}
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res = EmitMoveDoubleWordToSide(context, res, 0, op.Vd);
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context.Copy(d, EmitDoubleWordInsert(context, d, res, op.Vd));
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}
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else
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{
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int elems = op.GetBytesCount() >> op.Size;
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(int Qx, int Ix)[] tableTuples = new (int, int)[length];
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for (int i = 0; i < length; i++)
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{
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tableTuples[i] = GetQuadwordAndSubindex(op.Vn + i, op.RegisterSize);
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}
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int byteLength = length * 8;
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Operand res = GetVecA32(op.Qd);
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Operand m = GetVecA32(op.Qm);
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for (int index = 0; index < elems; index++)
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{
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Operand selectedIndex = context.ZeroExtend8(OperandType.I32, context.VectorExtract8(m, index + op.Im));
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Operand inRange = context.ICompareLess(selectedIndex, Const(byteLength));
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Operand elemRes = default; // Note: This is I64 for ease of calculation.
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// TODO: Branching rather than conditional select.
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// Get indexed byte.
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// To simplify (ha) the il, we get bytes from every vector and use a nested conditional select to choose the right result.
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// This does have to extract `length` times for every element but certainly not as bad as it could be.
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// Which vector number is the index on.
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Operand vecIndex = context.ShiftRightUI(selectedIndex, Const(3));
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// What should we shift by to extract it.
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Operand subVecIndexShift = context.ShiftLeft(context.BitwiseAnd(selectedIndex, Const(7)), Const(3));
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for (int i = 0; i < length; i++)
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{
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(int qx, int ix) = tableTuples[i];
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// Get the whole vector, we'll get a byte out of it.
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Operand lookupResult;
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if (qx == op.Qd)
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{
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// Result contains the current state of the vector.
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lookupResult = context.VectorExtract(OperandType.I64, res, ix);
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}
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else
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{
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lookupResult = EmitVectorExtract32(context, qx, ix, 3, false); // I64
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}
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lookupResult = context.ShiftRightUI(lookupResult, subVecIndexShift); // Get the relevant byte from this vector.
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if (i == 0)
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{
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elemRes = lookupResult; // First result is always default.
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}
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else
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{
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Operand isThisElem = context.ICompareEqual(vecIndex, Const(i));
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elemRes = context.ConditionalSelect(isThisElem, lookupResult, elemRes);
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}
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}
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Operand fallback = (extension) ? context.ZeroExtend32(OperandType.I64, EmitVectorExtract32(context, op.Qd, index + op.Id, 0, false)) : Const(0L);
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res = EmitVectorInsert(context, res, context.ConditionalSelect(inRange, elemRes, fallback), index + op.Id, 0);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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}
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public static void Vtrn(ArmEmitterContext context)
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{
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OpCode32SimdCmpZ op = (OpCode32SimdCmpZ)context.CurrOp;
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if (Optimizations.UseSsse3)
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{
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EmitVectorShuffleOpSimd32(context, (m, d) =>
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{
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Operand mask = default;
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if (op.Size < 3)
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{
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long maskE0 = EvenMasks[op.Size];
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long maskE1 = OddMasks[op.Size];
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mask = X86GetScalar(context, maskE0);
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mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
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}
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if (op.Size < 3)
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{
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d = context.AddIntrinsic(Intrinsic.X86Pshufb, d, mask);
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m = context.AddIntrinsic(Intrinsic.X86Pshufb, m, mask);
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}
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Operand resD = context.AddIntrinsic(X86PunpcklInstruction[op.Size], d, m);
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Operand resM = context.AddIntrinsic(X86PunpckhInstruction[op.Size], d, m);
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return (resM, resD);
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});
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}
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else
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{
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int elems = op.GetBytesCount() >> op.Size;
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int pairs = elems >> 1;
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bool overlap = op.Qm == op.Qd;
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Operand resD = GetVecA32(op.Qd);
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Operand resM = GetVecA32(op.Qm);
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for (int index = 0; index < pairs; index++)
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{
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int pairIndex = index << 1;
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Operand d2 = EmitVectorExtract32(context, op.Qd, pairIndex + 1 + op.Id, op.Size, false);
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Operand m1 = EmitVectorExtract32(context, op.Qm, pairIndex + op.Im, op.Size, false);
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resD = EmitVectorInsert(context, resD, m1, pairIndex + 1 + op.Id, op.Size);
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if (overlap)
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{
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resM = resD;
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}
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resM = EmitVectorInsert(context, resM, d2, pairIndex + op.Im, op.Size);
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if (overlap)
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{
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resD = resM;
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}
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}
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context.Copy(GetVecA32(op.Qd), resD);
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if (!overlap)
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{
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context.Copy(GetVecA32(op.Qm), resM);
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}
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}
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}
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public static void Vzip(ArmEmitterContext context)
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{
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OpCode32SimdCmpZ op = (OpCode32SimdCmpZ)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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EmitVectorShuffleOpSimd32(context, (m, d) =>
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{
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if (op.RegisterSize == RegisterSize.Simd128)
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{
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Operand resD = context.AddIntrinsic(X86PunpcklInstruction[op.Size], d, m);
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Operand resM = context.AddIntrinsic(X86PunpckhInstruction[op.Size], d, m);
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return (resM, resD);
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}
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else
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{
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Operand res = context.AddIntrinsic(X86PunpcklInstruction[op.Size], d, m);
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Operand resD = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, res, context.VectorZero());
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Operand resM = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, res, context.VectorZero());
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return (resM, resD);
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}
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});
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|
}
|
|
else
|
|
{
|
|
int elems = op.GetBytesCount() >> op.Size;
|
|
int pairs = elems >> 1;
|
|
|
|
bool overlap = op.Qm == op.Qd;
|
|
|
|
Operand resD = GetVecA32(op.Qd);
|
|
Operand resM = GetVecA32(op.Qm);
|
|
|
|
for (int index = 0; index < pairs; index++)
|
|
{
|
|
int pairIndex = index << 1;
|
|
Operand dRowD = EmitVectorExtract32(context, op.Qd, index + op.Id, op.Size, false);
|
|
Operand mRowD = EmitVectorExtract32(context, op.Qm, index + op.Im, op.Size, false);
|
|
|
|
Operand dRowM = EmitVectorExtract32(context, op.Qd, index + op.Id + pairs, op.Size, false);
|
|
Operand mRowM = EmitVectorExtract32(context, op.Qm, index + op.Im + pairs, op.Size, false);
|
|
|
|
resD = EmitVectorInsert(context, resD, dRowD, pairIndex + op.Id, op.Size);
|
|
resD = EmitVectorInsert(context, resD, mRowD, pairIndex + 1 + op.Id, op.Size);
|
|
|
|
if (overlap)
|
|
{
|
|
resM = resD;
|
|
}
|
|
|
|
resM = EmitVectorInsert(context, resM, dRowM, pairIndex + op.Im, op.Size);
|
|
resM = EmitVectorInsert(context, resM, mRowM, pairIndex + 1 + op.Im, op.Size);
|
|
|
|
if (overlap)
|
|
{
|
|
resD = resM;
|
|
}
|
|
}
|
|
|
|
context.Copy(GetVecA32(op.Qd), resD);
|
|
if (!overlap)
|
|
{
|
|
context.Copy(GetVecA32(op.Qm), resM);
|
|
}
|
|
}
|
|
}
|
|
|
|
public static void Vuzp(ArmEmitterContext context)
|
|
{
|
|
OpCode32SimdCmpZ op = (OpCode32SimdCmpZ)context.CurrOp;
|
|
|
|
if (Optimizations.UseSsse3)
|
|
{
|
|
EmitVectorShuffleOpSimd32(context, (m, d) =>
|
|
{
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
|
{
|
|
Operand mask = default;
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
long maskE0 = EvenMasks[op.Size];
|
|
long maskE1 = OddMasks[op.Size];
|
|
|
|
mask = X86GetScalar(context, maskE0);
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
|
|
d = context.AddIntrinsic(Intrinsic.X86Pshufb, d, mask);
|
|
m = context.AddIntrinsic(Intrinsic.X86Pshufb, m, mask);
|
|
}
|
|
|
|
Operand resD = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, d, m);
|
|
Operand resM = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, d, m);
|
|
|
|
return (resM, resD);
|
|
}
|
|
else
|
|
{
|
|
Intrinsic punpcklInst = X86PunpcklInstruction[op.Size];
|
|
|
|
Operand res = context.AddIntrinsic(punpcklInst, d, m);
|
|
|
|
if (op.Size < 2)
|
|
{
|
|
long maskE0 = _masksE0_Uzp[op.Size];
|
|
long maskE1 = _masksE1_Uzp[op.Size];
|
|
|
|
Operand mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
|
|
res = context.AddIntrinsic(Intrinsic.X86Pshufb, res, mask);
|
|
}
|
|
|
|
Operand resD = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, res, context.VectorZero());
|
|
Operand resM = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, res, context.VectorZero());
|
|
|
|
return (resM, resD);
|
|
}
|
|
});
|
|
}
|
|
else
|
|
{
|
|
int elems = op.GetBytesCount() >> op.Size;
|
|
int pairs = elems >> 1;
|
|
|
|
bool overlap = op.Qm == op.Qd;
|
|
|
|
Operand resD = GetVecA32(op.Qd);
|
|
Operand resM = GetVecA32(op.Qm);
|
|
|
|
for (int index = 0; index < elems; index++)
|
|
{
|
|
Operand dIns, mIns;
|
|
if (index >= pairs)
|
|
{
|
|
int pairIndex = index - pairs;
|
|
dIns = EmitVectorExtract32(context, op.Qm, (pairIndex << 1) + op.Im, op.Size, false);
|
|
mIns = EmitVectorExtract32(context, op.Qm, ((pairIndex << 1) | 1) + op.Im, op.Size, false);
|
|
}
|
|
else
|
|
{
|
|
dIns = EmitVectorExtract32(context, op.Qd, (index << 1) + op.Id, op.Size, false);
|
|
mIns = EmitVectorExtract32(context, op.Qd, ((index << 1) | 1) + op.Id, op.Size, false);
|
|
}
|
|
|
|
resD = EmitVectorInsert(context, resD, dIns, index + op.Id, op.Size);
|
|
|
|
if (overlap)
|
|
{
|
|
resM = resD;
|
|
}
|
|
|
|
resM = EmitVectorInsert(context, resM, mIns, index + op.Im, op.Size);
|
|
|
|
if (overlap)
|
|
{
|
|
resD = resM;
|
|
}
|
|
}
|
|
|
|
context.Copy(GetVecA32(op.Qd), resD);
|
|
if (!overlap)
|
|
{
|
|
context.Copy(GetVecA32(op.Qm), resM);
|
|
}
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorShuffleOpSimd32(ArmEmitterContext context, Func<Operand, Operand, (Operand, Operand)> shuffleFunc)
|
|
{
|
|
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
|
|
|
|
Operand m = GetVecA32(op.Qm);
|
|
Operand d = GetVecA32(op.Qd);
|
|
Operand initialM = m;
|
|
Operand initialD = d;
|
|
|
|
if (!op.Q) // Register swap: move relevant doubleword to side 0, for consistency.
|
|
{
|
|
m = EmitMoveDoubleWordToSide(context, m, op.Vm, 0);
|
|
d = EmitMoveDoubleWordToSide(context, d, op.Vd, 0);
|
|
}
|
|
|
|
(Operand resM, Operand resD) = shuffleFunc(m, d);
|
|
|
|
bool overlap = op.Qm == op.Qd;
|
|
|
|
if (!op.Q) // Register insert.
|
|
{
|
|
resM = EmitDoubleWordInsert(context, initialM, EmitMoveDoubleWordToSide(context, resM, 0, op.Vm), op.Vm);
|
|
resD = EmitDoubleWordInsert(context, overlap ? resM : initialD, EmitMoveDoubleWordToSide(context, resD, 0, op.Vd), op.Vd);
|
|
}
|
|
|
|
if (!overlap)
|
|
{
|
|
context.Copy(initialM, resM);
|
|
}
|
|
|
|
context.Copy(initialD, resD);
|
|
}
|
|
}
|
|
}
|