mirror of
https://github.com/ryujinx-mirror/ryujinx.git
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814f75142e
* Implemented in IR the managed methods of the Saturating region ... ... of the SoftFallback class (the SatQ ones). The need to natively manage the Fpcr and Fpsr system registers is still a fact. Contributes to https://github.com/Ryujinx/Ryujinx/issues/2917 ; I will open another PR to implement in Intrinsics-branchless the methods of the Saturation region as well (the SatXXXToXXX ones). All instructions involved have been tested locally in both release and debug modes, in both lowcq and highcq. * Ptc.InternalVersion = 3665 * Addressed PR feedback. * Implemented in IR the managed methods of the ShlReg region of the SoftFallback class. It also includes the last two SatQ ones (following up on https://github.com/Ryujinx/Ryujinx/pull/3665). All instructions involved have been tested locally in both release and debug modes, in both lowcq and highcq. * Fpsr and Fpcr freed. Handling/isolation of Fpsr and Fpcr via register for IR and via memory for Tests and Threads, with synchronization to context exchanges (explicit for SoftFloat); without having to call managed methods. Thanks to the inlining work of the previous two PRs and others in this. Tests performed locally in both release and debug modes, in both lowcq and highcq, with FastFP to true and false (explicit FP tests included). Tested with the title Tony Hawk's PS. Depends on shlreg. * Update InstEmitSimdHelper.cs * De-magic Masks. Remove the Stride and Len flags; Fpsr.NZCV are A32 only, then moved to Fpscr: this leads to emitting less IR in reference to Get/Set Fpsr/Fpcr/Fpscr methods in reference to Mrs/Msr (A64) and Vmrs/Vmsr (A32) instructions. * Addressed PR feedback.
326 lines
11 KiB
C#
326 lines
11 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using System.Reflection;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void Mcr(ArmEmitterContext context)
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{
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OpCode32System op = (OpCode32System)context.CurrOp;
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if (op.Coproc != 15 || op.Opc1 != 0)
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{
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InstEmit.Und(context);
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return;
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}
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MethodInfo info;
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switch (op.CRn)
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{
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case 13: // Process and Thread Info.
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if (op.CRm != 0)
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{
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throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
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}
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switch (op.Opc2)
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{
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case 2:
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info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl032)); break;
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default:
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throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
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}
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break;
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case 7:
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switch (op.CRm) // Cache and Memory barrier.
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{
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case 10:
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switch (op.Opc2)
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{
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case 5: // Data Memory Barrier Register.
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return; // No-op.
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default:
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throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16} (0x{op.RawOpCode:X}).");
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}
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default:
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throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16} (0x{op.RawOpCode:X}).");
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}
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default:
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throw new NotImplementedException($"Unknown MRC 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
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}
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context.Call(info, GetIntA32(context, op.Rt));
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}
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public static void Mrc(ArmEmitterContext context)
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{
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OpCode32System op = (OpCode32System)context.CurrOp;
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if (op.Coproc != 15 || op.Opc1 != 0)
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{
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InstEmit.Und(context);
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return;
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}
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MethodInfo info;
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switch (op.CRn)
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{
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case 13: // Process and Thread Info.
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if (op.CRm != 0)
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{
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throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
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}
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switch (op.Opc2)
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{
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case 2:
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info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidrEl032)); break;
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case 3:
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info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidr32)); break;
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default:
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throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
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}
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break;
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default:
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throw new NotImplementedException($"Unknown MRC 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
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}
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if (op.Rt == RegisterAlias.Aarch32Pc)
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{
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// Special behavior: copy NZCV flags into APSR.
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EmitSetNzcv(context, context.Call(info));
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return;
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}
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else
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{
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SetIntA32(context, op.Rt, context.Call(info));
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}
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}
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public static void Mrrc(ArmEmitterContext context)
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{
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OpCode32System op = (OpCode32System)context.CurrOp;
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if (op.Coproc != 15)
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{
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InstEmit.Und(context);
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return;
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}
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int opc = op.MrrcOp;
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MethodInfo info;
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switch (op.CRm)
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{
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case 14: // Timer.
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switch (opc)
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{
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case 0:
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info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break;
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default:
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throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
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}
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break;
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default:
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throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
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}
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Operand result = context.Call(info);
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SetIntA32(context, op.Rt, context.ConvertI64ToI32(result));
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SetIntA32(context, op.CRn, context.ConvertI64ToI32(context.ShiftRightUI(result, Const(32))));
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}
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public static void Mrs(ArmEmitterContext context)
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{
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OpCode32Mrs op = (OpCode32Mrs)context.CurrOp;
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if (op.R)
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{
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throw new NotImplementedException("SPSR");
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}
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else
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{
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Operand spsr = context.ShiftLeft(GetFlag(PState.VFlag), Const((int)PState.VFlag));
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spsr = context.BitwiseOr(spsr, context.ShiftLeft(GetFlag(PState.CFlag), Const((int)PState.CFlag)));
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spsr = context.BitwiseOr(spsr, context.ShiftLeft(GetFlag(PState.ZFlag), Const((int)PState.ZFlag)));
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spsr = context.BitwiseOr(spsr, context.ShiftLeft(GetFlag(PState.NFlag), Const((int)PState.NFlag)));
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spsr = context.BitwiseOr(spsr, context.ShiftLeft(GetFlag(PState.QFlag), Const((int)PState.QFlag)));
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// TODO: Remaining flags.
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SetIntA32(context, op.Rd, spsr);
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}
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}
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public static void Msr(ArmEmitterContext context)
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{
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OpCode32MsrReg op = (OpCode32MsrReg)context.CurrOp;
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if (op.R)
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{
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throw new NotImplementedException("SPSR");
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}
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else
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{
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if ((op.Mask & 8) != 0)
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{
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Operand value = GetIntA32(context, op.Rn);
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EmitSetNzcv(context, value);
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Operand q = context.BitwiseAnd(context.ShiftRightUI(value, Const((int)PState.QFlag)), Const(1));
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SetFlag(context, PState.QFlag, q);
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}
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if ((op.Mask & 4) != 0)
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{
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throw new NotImplementedException("APSR_g");
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}
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if ((op.Mask & 2) != 0)
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{
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throw new NotImplementedException("CPSR_x");
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}
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if ((op.Mask & 1) != 0)
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{
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throw new NotImplementedException("CPSR_c");
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}
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}
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}
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public static void Nop(ArmEmitterContext context) { }
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public static void Vmrs(ArmEmitterContext context)
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{
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OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
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if (op.Rt == RegisterAlias.Aarch32Pc && op.Sreg == 0b0001)
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{
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// Special behavior: copy NZCV flags into APSR.
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SetFlag(context, PState.VFlag, GetFpFlag(FPState.VFlag));
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SetFlag(context, PState.CFlag, GetFpFlag(FPState.CFlag));
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SetFlag(context, PState.ZFlag, GetFpFlag(FPState.ZFlag));
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SetFlag(context, PState.NFlag, GetFpFlag(FPState.NFlag));
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return;
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}
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switch (op.Sreg)
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{
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case 0b0000: // FPSID
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throw new NotImplementedException("Supervisor Only");
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case 0b0001: // FPSCR
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EmitGetFpscr(context); return;
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case 0b0101: // MVFR2
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throw new NotImplementedException("MVFR2");
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case 0b0110: // MVFR1
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throw new NotImplementedException("MVFR1");
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case 0b0111: // MVFR0
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throw new NotImplementedException("MVFR0");
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case 0b1000: // FPEXC
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throw new NotImplementedException("Supervisor Only");
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default:
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throw new NotImplementedException($"Unknown VMRS 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
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}
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}
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public static void Vmsr(ArmEmitterContext context)
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{
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OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
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switch (op.Sreg)
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{
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case 0b0000: // FPSID
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throw new NotImplementedException("Supervisor Only");
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case 0b0001: // FPSCR
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EmitSetFpscr(context); return;
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case 0b0101: // MVFR2
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throw new NotImplementedException("MVFR2");
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case 0b0110: // MVFR1
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throw new NotImplementedException("MVFR1");
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case 0b0111: // MVFR0
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throw new NotImplementedException("MVFR0");
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case 0b1000: // FPEXC
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throw new NotImplementedException("Supervisor Only");
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default:
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throw new NotImplementedException($"Unknown VMSR 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
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}
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}
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private static void EmitSetNzcv(ArmEmitterContext context, Operand t)
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{
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Operand v = context.BitwiseAnd(context.ShiftRightUI(t, Const((int)PState.VFlag)), Const(1));
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Operand c = context.BitwiseAnd(context.ShiftRightUI(t, Const((int)PState.CFlag)), Const(1));
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Operand z = context.BitwiseAnd(context.ShiftRightUI(t, Const((int)PState.ZFlag)), Const(1));
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Operand n = context.BitwiseAnd(context.ShiftRightUI(t, Const((int)PState.NFlag)), Const(1));
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SetFlag(context, PState.VFlag, v);
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SetFlag(context, PState.CFlag, c);
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SetFlag(context, PState.ZFlag, z);
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SetFlag(context, PState.NFlag, n);
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}
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private static void EmitGetFpscr(ArmEmitterContext context)
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{
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OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
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Operand fpscr = Const(0);
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for (int flag = 0; flag < RegisterConsts.FpFlagsCount; flag++)
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{
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if (FPSCR.Mask.HasFlag((FPSCR)(1u << flag)))
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{
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fpscr = context.BitwiseOr(fpscr, context.ShiftLeft(GetFpFlag((FPState)flag), Const(flag)));
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}
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}
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SetIntA32(context, op.Rt, fpscr);
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}
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private static void EmitSetFpscr(ArmEmitterContext context)
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{
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OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
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Operand fpscr = GetIntA32(context, op.Rt);
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for (int flag = 0; flag < RegisterConsts.FpFlagsCount; flag++)
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{
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if (FPSCR.Mask.HasFlag((FPSCR)(1u << flag)))
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{
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SetFpFlag(context, (FPState)flag, context.BitwiseAnd(context.ShiftRightUI(fpscr, Const(flag)), Const(1)));
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}
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}
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}
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}
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}
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