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89ccec197e
* Implement VMOVL and VORR.I32 AArch32 SIMD instructions * Rename <dt> to <size> on test description * Rename Widen to Long and improve VMOVL implementation a bit
88 lines
2.9 KiB
C#
88 lines
2.9 KiB
C#
namespace ARMeilleure.Decoders
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{
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public static class OpCodeSimdHelper
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{
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public static (long Immediate, int Size) GetSimdImmediateAndSize(int cMode, int op, long imm)
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{
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int modeLow = cMode & 1;
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int modeHigh = cMode >> 1;
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int size = 0;
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if (modeHigh == 0b111)
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{
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switch (op | (modeLow << 1))
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{
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case 0:
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// 64-bits Immediate.
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// Transform abcd efgh into abcd efgh abcd efgh ...
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size = 3;
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imm = (long)((ulong)imm * 0x0101010101010101);
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break;
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case 1:
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// 64-bits Immediate.
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// Transform abcd efgh into aaaa aaaa bbbb bbbb ...
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size = 3;
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imm = (imm & 0xf0) >> 4 | (imm & 0x0f) << 4;
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imm = (imm & 0xcc) >> 2 | (imm & 0x33) << 2;
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imm = (imm & 0xaa) >> 1 | (imm & 0x55) << 1;
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imm = (long)((ulong)imm * 0x8040201008040201);
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imm = (long)((ulong)imm & 0x8080808080808080);
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imm |= imm >> 4;
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imm |= imm >> 2;
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imm |= imm >> 1;
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break;
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case 2:
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// 2 x 32-bits floating point Immediate.
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size = 3;
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imm = (long)DecoderHelper.Imm8ToFP32Table[(int)imm];
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imm |= imm << 32;
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break;
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case 3:
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// 64-bits floating point Immediate.
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size = 3;
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imm = (long)DecoderHelper.Imm8ToFP64Table[(int)imm];
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break;
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}
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}
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else if ((modeHigh & 0b110) == 0b100)
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{
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// 16-bits shifted Immediate.
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size = 1; imm <<= (modeHigh & 1) << 3;
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}
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else if ((modeHigh & 0b100) == 0b000)
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{
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// 32-bits shifted Immediate.
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size = 2; imm <<= modeHigh << 3;
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}
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else if ((modeHigh & 0b111) == 0b110)
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{
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// 32-bits shifted Immediate (fill with ones).
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size = 2; imm = ShlOnes(imm, 8 << modeLow);
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}
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else
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{
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// 8-bits without shift.
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size = 0;
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}
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return (imm, size);
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}
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private static long ShlOnes(long value, int shift)
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{
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if (shift != 0)
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{
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return value << shift | (long)(ulong.MaxValue >> (64 - shift));
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}
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else
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{
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return value;
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}
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}
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}
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}
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