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https://github.com/ryujinx-mirror/ryujinx.git
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17620d18db
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as short-hands for `F+VL` and `F+VL+DQ`. * ARMeilleure: Add initial support for EVEX instruction encoding Does not implement rounding, or exception controls. * ARMeilleure: Add `X86Vpternlogd` Accelerates the vector-`Not` instruction. * ARMeilleure: Add check for `OSXSAVE` for AVX{2,512} * ARMeilleure: Add check for `XCR0` flags Add XCR0 register checks for AVX and AVX512F, following the guidelines from section 14.3 and 15.2 from the Intel Architecture Software Developer's Manual. * ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting * ARMeilleure: Move XCR0 procedure to GetXcr0Eax * ARMeilleure: Add `XCR0` to `FeatureInfo` structure * ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly Avoids an additional allocation * ARMeilleure: Formatting fixes * ARMeilleure: Fix EVEX encoding src2 register index > Just like in VEX prefix, vvvv is provided in inverted form. * ARMeilleure: Add `X86Vpternlogd` acceleration to `Vmvn_I` Passes unit tests, verified instruction utilization * ARMeilleure: Fix EVEX register operand designations Operand 2 was being sourced improperly. EVEX encoded instructions source their operands like so: Operand 1: ModRM:reg Operand 2: EVEX.vvvvv Operand 3: ModRM:r/m Operand 4: Imm This fixes the improper register designations when emitting vpternlog. Now "dest", "src1", "src2" arguments emit in the proper order in EVEX instructions. * ARMeilleure: Add `X86Vpternlogd` acceleration to `Orn_V` * ARMeilleure: PTC version bump * ARMeilleure: Update EVEX encoding Debug.Assert to Debug.Fail * ARMeilleure: Update EVEX encoding comment capitalization
137 lines
No EOL
5.2 KiB
C#
137 lines
No EOL
5.2 KiB
C#
using Ryujinx.Memory;
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using System;
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using System.Runtime.InteropServices;
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using System.Runtime.Intrinsics.X86;
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namespace ARMeilleure.CodeGen.X86
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{
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static class HardwareCapabilities
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{
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private delegate uint GetXcr0();
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static HardwareCapabilities()
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{
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if (!X86Base.IsSupported)
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{
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return;
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}
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(int maxNum, _, _, _) = X86Base.CpuId(0x00000000, 0x00000000);
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(_, _, int ecx1, int edx1) = X86Base.CpuId(0x00000001, 0x00000000);
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FeatureInfo1Edx = (FeatureFlags1Edx)edx1;
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FeatureInfo1Ecx = (FeatureFlags1Ecx)ecx1;
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if (maxNum >= 7)
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{
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(_, int ebx7, int ecx7, _) = X86Base.CpuId(0x00000007, 0x00000000);
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FeatureInfo7Ebx = (FeatureFlags7Ebx)ebx7;
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FeatureInfo7Ecx = (FeatureFlags7Ecx)ecx7;
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}
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Xcr0InfoEax = (Xcr0FlagsEax)GetXcr0Eax();
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}
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private static uint GetXcr0Eax()
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{
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ReadOnlySpan<byte> asmGetXcr0 = new byte[]
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{
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0x31, 0xc9, // xor ecx, ecx
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0xf, 0x01, 0xd0, // xgetbv
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0xc3, // ret
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};
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using MemoryBlock memGetXcr0 = new MemoryBlock((ulong)asmGetXcr0.Length);
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memGetXcr0.Write(0, asmGetXcr0);
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memGetXcr0.Reprotect(0, (ulong)asmGetXcr0.Length, MemoryPermission.ReadAndExecute);
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var fGetXcr0 = Marshal.GetDelegateForFunctionPointer<GetXcr0>(memGetXcr0.Pointer);
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return fGetXcr0();
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}
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[Flags]
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public enum FeatureFlags1Edx
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{
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Sse = 1 << 25,
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Sse2 = 1 << 26
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}
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[Flags]
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public enum FeatureFlags1Ecx
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{
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Sse3 = 1 << 0,
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Pclmulqdq = 1 << 1,
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Ssse3 = 1 << 9,
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Fma = 1 << 12,
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Sse41 = 1 << 19,
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Sse42 = 1 << 20,
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Popcnt = 1 << 23,
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Aes = 1 << 25,
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Osxsave = 1 << 27,
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Avx = 1 << 28,
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F16c = 1 << 29
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}
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[Flags]
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public enum FeatureFlags7Ebx
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{
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Avx2 = 1 << 5,
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Avx512f = 1 << 16,
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Avx512dq = 1 << 17,
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Sha = 1 << 29,
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Avx512bw = 1 << 30,
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Avx512vl = 1 << 31
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}
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[Flags]
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public enum FeatureFlags7Ecx
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{
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Gfni = 1 << 8,
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}
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[Flags]
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public enum Xcr0FlagsEax
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{
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Sse = 1 << 1,
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YmmHi128 = 1 << 2,
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Opmask = 1 << 5,
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ZmmHi256 = 1 << 6,
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Hi16Zmm = 1 << 7
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}
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public static FeatureFlags1Edx FeatureInfo1Edx { get; }
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public static FeatureFlags1Ecx FeatureInfo1Ecx { get; }
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public static FeatureFlags7Ebx FeatureInfo7Ebx { get; } = 0;
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public static FeatureFlags7Ecx FeatureInfo7Ecx { get; } = 0;
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public static Xcr0FlagsEax Xcr0InfoEax { get; } = 0;
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public static bool SupportsSse => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse);
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public static bool SupportsSse2 => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse2);
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public static bool SupportsSse3 => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Sse3);
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public static bool SupportsPclmulqdq => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Pclmulqdq);
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public static bool SupportsSsse3 => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Ssse3);
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public static bool SupportsFma => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Fma);
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public static bool SupportsSse41 => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Sse41);
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public static bool SupportsSse42 => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Sse42);
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public static bool SupportsPopcnt => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Popcnt);
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public static bool SupportsAesni => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Aes);
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public static bool SupportsAvx => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Avx | FeatureFlags1Ecx.Osxsave) && Xcr0InfoEax.HasFlag(Xcr0FlagsEax.Sse | Xcr0FlagsEax.YmmHi128);
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public static bool SupportsAvx2 => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx2) && SupportsAvx;
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public static bool SupportsAvx512F => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx512f) && FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Osxsave)
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&& Xcr0InfoEax.HasFlag(Xcr0FlagsEax.Sse | Xcr0FlagsEax.YmmHi128 | Xcr0FlagsEax.Opmask | Xcr0FlagsEax.ZmmHi256 | Xcr0FlagsEax.Hi16Zmm);
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public static bool SupportsAvx512Vl => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx512vl) && SupportsAvx512F;
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public static bool SupportsAvx512Bw => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx512bw) && SupportsAvx512F;
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public static bool SupportsAvx512Dq => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx512dq) && SupportsAvx512F;
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public static bool SupportsF16c => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.F16c);
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public static bool SupportsSha => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Sha);
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public static bool SupportsGfni => FeatureInfo7Ecx.HasFlag(FeatureFlags7Ecx.Gfni);
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public static bool ForceLegacySse { get; set; }
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public static bool SupportsVexEncoding => SupportsAvx && !ForceLegacySse;
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public static bool SupportsEvexEncoding => SupportsAvx512F && !ForceLegacySse;
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}
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} |