ryujinx-mirror/ARMeilleure/Translation
gdkchan 0c87bf9ea4
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
* Refactor CPU interface

* Use IExecutionContext interface on SVC handler, change how CPU interrupts invokes the handlers

* Make CpuEngine take a ITickSource rather than returning one

The previous implementation had the scenario where the CPU engine had to implement the tick source in mind, like for example, when we have a hypervisor and the game can read CNTPCT on the host directly. However given that we need to do conversion due to different frequencies anyway, it's not worth it. It's better to just let the user pass the tick source and redirect any reads to CNTPCT to the user tick source

* XML docs for the public interfaces

* PPTC invalidation due to NativeInterface function name changes

* Fix build of the CPU tests

* PR feedback
2022-05-31 16:29:35 -03:00
..
Cache misc: Migrate usage of RuntimeInformation to OperatingSystem (#2901) 2021-12-04 20:02:30 -03:00
PTC Refactor CPU interface to allow the implementation of other CPU emulators (#3362) 2022-05-31 16:29:35 -03:00
ArmEmitterContext.cs ARMeilleure: Thumb support (All T16 instructions) (#3105) 2022-02-17 19:39:45 -03:00
Compiler.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
CompilerContext.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
CompilerOptions.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00
ControlFlowGraph.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
DelegateHelper.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
DelegateInfo.cs PPTC Follow-up. (#1712) 2020-12-17 20:32:09 +01:00
Delegates.cs Refactor CPU interface to allow the implementation of other CPU emulators (#3362) 2022-05-31 16:29:35 -03:00
DispatcherFunction.cs Add multi-level function table (#2228) 2021-05-29 18:06:28 -03:00
Dominance.cs Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931) 2020-02-17 22:30:54 +01:00
EmitterContext.cs Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 2022-01-21 12:47:34 -03:00
GuestFunction.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
IntervalTree.cs Support memory aliasing (#2954) 2022-05-02 20:30:02 -03:00
RegisterToLocal.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
RegisterUsage.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
RejitRequest.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
SsaConstruction.cs Collapse AsSpan().Slice(..) calls into AsSpan(..) (#3145) 2022-02-22 10:32:10 -03:00
SsaDeconstruction.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
TranslatedFunction.cs Add inlined on translation call counting (#2190) 2021-04-18 23:43:53 +02:00
Translator.cs ARMeilleure: Implement single stepping (#3133) 2022-02-22 11:11:42 -03:00
TranslatorCache.cs Enable CPU JIT cache invalidation (#2965) 2022-02-18 02:53:18 +01:00
TranslatorStubs.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00