mirror of
https://github.com/ryujinx-mirror/ryujinx.git
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582 lines
20 KiB
C#
582 lines
20 KiB
C#
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using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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using Func1I = Func<Operand, Operand>;
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using Func2I = Func<Operand, Operand, Operand>;
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using Func3I = Func<Operand, Operand, Operand, Operand>;
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static class InstEmitSimdHelper32
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{
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public static (int, int) GetQuadwordAndSubindex(int index, RegisterSize size)
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{
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switch (size)
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{
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case RegisterSize.Simd128:
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return (index >> 1, 0);
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case RegisterSize.Simd64:
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case RegisterSize.Int64:
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return (index >> 1, index & 1);
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case RegisterSize.Int32:
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return (index >> 2, index & 3);
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}
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throw new ArgumentException("Unrecognized Vector Register Size.");
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}
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public static Operand ExtractScalar(ArmEmitterContext context, OperandType type, int reg)
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{
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Debug.Assert(type != OperandType.V128);
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if (type == OperandType.FP64 || type == OperandType.I64)
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{
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// From dreg.
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return context.VectorExtract(type, GetVecA32(reg >> 1), reg & 1);
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}
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else
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{
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// From sreg.
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return context.VectorExtract(type, GetVecA32(reg >> 2), reg & 3);
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}
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}
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public static void InsertScalar(ArmEmitterContext context, int reg, Operand value)
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{
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Debug.Assert(value.Type != OperandType.V128);
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Operand vec, insert;
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if (value.Type == OperandType.FP64 || value.Type == OperandType.I64)
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{
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// From dreg.
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vec = GetVecA32(reg >> 1);
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insert = context.VectorInsert(vec, value, reg & 1);
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}
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else
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{
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// From sreg.
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vec = GetVecA32(reg >> 2);
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insert = context.VectorInsert(vec, value, reg & 3);
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}
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context.Copy(vec, insert);
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}
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public static void EmitVectorImmUnaryOp32(ArmEmitterContext context, Func1I emit)
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{
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IOpCode32SimdImm op = (IOpCode32SimdImm)context.CurrOp;
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Operand imm = Const(op.Immediate);
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int elems = op.Elems;
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(int index, int subIndex) = GetQuadwordAndSubindex(op.Vd, op.RegisterSize);
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Operand vec = GetVecA32(index);
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Operand res = vec;
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for (int item = 0; item < elems; item++)
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{
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res = EmitVectorInsert(context, res, emit(imm), item + subIndex * elems, op.Size);
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}
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context.Copy(vec, res);
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}
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public static void EmitScalarUnaryOpF32(ArmEmitterContext context, Func1I emit)
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{
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OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
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OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
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Operand m = ExtractScalar(context, type, op.Vm);
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InsertScalar(context, op.Vd, emit(m));
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}
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public static void EmitScalarBinaryOpF32(ArmEmitterContext context, Func2I emit)
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{
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
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Operand n = ExtractScalar(context, type, op.Vn);
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Operand m = ExtractScalar(context, type, op.Vm);
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InsertScalar(context, op.Vd, emit(n, m));
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}
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public static void EmitScalarBinaryOpI32(ArmEmitterContext context, Func2I emit)
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{
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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OperandType type = (op.Size & 1) != 0 ? OperandType.I64 : OperandType.I32;
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if (op.Size < 2)
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{
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throw new NotSupportedException("Cannot perform a scalar SIMD operation on integers smaller than 32 bits.");
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}
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Operand n = ExtractScalar(context, type, op.Vn);
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Operand m = ExtractScalar(context, type, op.Vm);
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InsertScalar(context, op.Vd, emit(n, m));
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}
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public static void EmitScalarTernaryOpF32(ArmEmitterContext context, Func3I emit)
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{
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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OperandType type = (op.Size & 1) != 0 ? OperandType.FP64 : OperandType.FP32;
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Operand a = ExtractScalar(context, type, op.Vd);
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Operand n = ExtractScalar(context, type, op.Vn);
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Operand m = ExtractScalar(context, type, op.Vm);
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InsertScalar(context, op.Vd, emit(a, n, m));
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}
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public static void EmitVectorUnaryOpF32(ArmEmitterContext context, Func1I emit)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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int sizeF = op.Size & 1;
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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int elems = op.GetBytesCount() >> sizeF + 2;
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Operand res = GetVecA32(op.Qd);
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for (int index = 0; index < elems; index++)
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{
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Operand me = context.VectorExtract(type, GetVecA32(op.Qm), op.Fm + index);
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res = context.VectorInsert(res, emit(me), op.Fd + index);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorBinaryOpF32(ArmEmitterContext context, Func2I emit)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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int sizeF = op.Size & 1;
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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int elems = op.GetBytesCount() >> (sizeF + 2);
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Operand res = GetVecA32(op.Qd);
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for (int index = 0; index < elems; index++)
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{
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Operand ne = context.VectorExtract(type, GetVecA32(op.Qn), op.Fn + index);
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Operand me = context.VectorExtract(type, GetVecA32(op.Qm), op.Fm + index);
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res = context.VectorInsert(res, emit(ne, me), op.Fd + index);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorTernaryOpF32(ArmEmitterContext context, Func3I emit)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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int sizeF = op.Size & 1;
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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int elems = op.GetBytesCount() >> sizeF + 2;
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Operand res = GetVecA32(op.Qd);
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for (int index = 0; index < elems; index++)
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{
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Operand de = context.VectorExtract(type, GetVecA32(op.Qd), op.Fd + index);
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Operand ne = context.VectorExtract(type, GetVecA32(op.Qn), op.Fn + index);
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Operand me = context.VectorExtract(type, GetVecA32(op.Qm), op.Fm + index);
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res = context.VectorInsert(res, emit(de, ne, me), op.Fd + index);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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// Integer
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public static void EmitVectorUnaryOpI32(ArmEmitterContext context, Func1I emit, bool signed)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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Operand res = GetVecA32(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(me), op.Id + index, op.Size);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorBinaryOpI32(ArmEmitterContext context, Func2I emit, bool signed)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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Operand res = GetVecA32(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed);
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(ne, me), op.Id + index, op.Size);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorTernaryOpI32(ArmEmitterContext context, Func3I emit, bool signed)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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Operand res = GetVecA32(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size, signed);
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Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed);
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(de, ne, me), op.Id + index, op.Size);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorUnaryOpSx32(ArmEmitterContext context, Func1I emit)
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{
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EmitVectorUnaryOpI32(context, emit, true);
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}
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public static void EmitVectorBinaryOpSx32(ArmEmitterContext context, Func2I emit)
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{
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EmitVectorBinaryOpI32(context, emit, true);
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}
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public static void EmitVectorTernaryOpSx32(ArmEmitterContext context, Func3I emit)
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{
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EmitVectorTernaryOpI32(context, emit, true);
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}
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public static void EmitVectorUnaryOpZx32(ArmEmitterContext context, Func1I emit)
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{
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EmitVectorUnaryOpI32(context, emit, false);
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}
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public static void EmitVectorBinaryOpZx32(ArmEmitterContext context, Func2I emit)
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{
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EmitVectorBinaryOpI32(context, emit, false);
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}
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public static void EmitVectorTernaryOpZx32(ArmEmitterContext context, Func3I emit)
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{
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EmitVectorTernaryOpI32(context, emit, false);
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}
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// Vector by scalar
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public static void EmitVectorByScalarOpF32(ArmEmitterContext context, Func2I emit)
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{
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OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
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int sizeF = op.Size & 1;
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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int elems = op.GetBytesCount() >> sizeF + 2;
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Operand m = ExtractScalar(context, type, op.Vm);
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Operand res = GetVecA32(op.Qd);
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for (int index = 0; index < elems; index++)
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{
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Operand ne = context.VectorExtract(type, GetVecA32(op.Qn), op.Fn + index);
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res = context.VectorInsert(res, emit(ne, m), op.Fd + index);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void EmitVectorByScalarOpI32(ArmEmitterContext context, Func2I emit, bool signed)
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{
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OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
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Operand m = EmitVectorExtract32(context, op.Vm >> (4 - op.Size), op.Vm & ((1 << (4 - op.Size)) - 1), op.Size, signed);
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Operand res = GetVecA32(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(ne, m), op.In + index, op.Size);
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}
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|||
|
|
|
|||
|
|
context.Copy(GetVecA32(op.Qd), res);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public static void EmitVectorsByScalarOpF32(ArmEmitterContext context, Func3I emit)
|
|||
|
|
{
|
|||
|
|
OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
|
|||
|
|
|
|||
|
|
int sizeF = op.Size & 1;
|
|||
|
|
|
|||
|
|
OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
|
|||
|
|
|
|||
|
|
int elems = op.GetBytesCount() >> sizeF + 2;
|
|||
|
|
|
|||
|
|
Operand m = ExtractScalar(context, type, op.Vm);
|
|||
|
|
|
|||
|
|
Operand res = GetVecA32(op.Qd);
|
|||
|
|
|
|||
|
|
for (int index = 0; index < elems; index++)
|
|||
|
|
{
|
|||
|
|
Operand de = context.VectorExtract(type, GetVecA32(op.Qd), op.Fd + index);
|
|||
|
|
Operand ne = context.VectorExtract(type, GetVecA32(op.Qn), op.Fn + index);
|
|||
|
|
|
|||
|
|
res = context.VectorInsert(res, emit(de, ne, m), op.Fd + index);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
context.Copy(GetVecA32(op.Qd), res);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public static void EmitVectorsByScalarOpI32(ArmEmitterContext context, Func3I emit, bool signed)
|
|||
|
|
{
|
|||
|
|
OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
|
|||
|
|
|
|||
|
|
Operand m = EmitVectorExtract32(context, op.Vm >> (4 - op.Size), op.Vm & ((1 << (4 - op.Size)) - 1), op.Size, signed);
|
|||
|
|
|
|||
|
|
Operand res = GetVecA32(op.Qd);
|
|||
|
|
|
|||
|
|
int elems = op.GetBytesCount() >> op.Size;
|
|||
|
|
|
|||
|
|
for (int index = 0; index < elems; index++)
|
|||
|
|
{
|
|||
|
|
Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size, signed);
|
|||
|
|
Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed);
|
|||
|
|
|
|||
|
|
res = EmitVectorInsert(context, res, emit(de, ne, m), op.Id + index, op.Size);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
context.Copy(GetVecA32(op.Qd), res);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Pairwise
|
|||
|
|
|
|||
|
|
public static void EmitVectorPairwiseOpF32(ArmEmitterContext context, Func2I emit)
|
|||
|
|
{
|
|||
|
|
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
|||
|
|
|
|||
|
|
int sizeF = op.Size & 1;
|
|||
|
|
|
|||
|
|
OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
|
|||
|
|
|
|||
|
|
int elems = op.GetBytesCount() >> (sizeF + 2);
|
|||
|
|
int pairs = elems >> 1;
|
|||
|
|
|
|||
|
|
Operand res = GetVecA32(op.Qd);
|
|||
|
|
Operand mvec = GetVecA32(op.Qm);
|
|||
|
|
Operand nvec = GetVecA32(op.Qn);
|
|||
|
|
|
|||
|
|
for (int index = 0; index < pairs; index++)
|
|||
|
|
{
|
|||
|
|
int pairIndex = index << 1;
|
|||
|
|
|
|||
|
|
Operand n1 = context.VectorExtract(type, nvec, op.Fn + pairIndex);
|
|||
|
|
Operand n2 = context.VectorExtract(type, nvec, op.Fn + pairIndex + 1);
|
|||
|
|
|
|||
|
|
res = context.VectorInsert(res, emit(n1, n2), op.Fd + index);
|
|||
|
|
|
|||
|
|
Operand m1 = context.VectorExtract(type, mvec, op.Fm + pairIndex);
|
|||
|
|
Operand m2 = context.VectorExtract(type, mvec, op.Fm + pairIndex + 1);
|
|||
|
|
|
|||
|
|
res = context.VectorInsert(res, emit(m1, m2), op.Fd + index + pairs);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
context.Copy(GetVecA32(op.Qd), res);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public static void EmitVectorPairwiseOpI32(ArmEmitterContext context, Func2I emit, bool signed)
|
|||
|
|
{
|
|||
|
|
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
|||
|
|
|
|||
|
|
int elems = op.GetBytesCount() >> op.Size;
|
|||
|
|
int pairs = elems >> 1;
|
|||
|
|
|
|||
|
|
Operand res = GetVecA32(op.Qd);
|
|||
|
|
|
|||
|
|
for (int index = 0; index < pairs; index++)
|
|||
|
|
{
|
|||
|
|
int pairIndex = index << 1;
|
|||
|
|
Operand n1 = EmitVectorExtract32(context, op.Qn, op.In + pairIndex, op.Size, signed);
|
|||
|
|
Operand n2 = EmitVectorExtract32(context, op.Qn, op.In + pairIndex + 1, op.Size, signed);
|
|||
|
|
|
|||
|
|
Operand m1 = EmitVectorExtract32(context, op.Qm, op.Im + pairIndex, op.Size, signed);
|
|||
|
|
Operand m2 = EmitVectorExtract32(context, op.Qm, op.Im + pairIndex + 1, op.Size, signed);
|
|||
|
|
|
|||
|
|
res = EmitVectorInsert(context, res, emit(n1, n2), op.Id + index, op.Size);
|
|||
|
|
res = EmitVectorInsert(context, res, emit(m1, m2), op.Id + index + pairs, op.Size);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
context.Copy(GetVecA32(op.Qd), res);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Narrow
|
|||
|
|
|
|||
|
|
public static void EmitVectorUnaryNarrowOp32(ArmEmitterContext context, Func1I emit)
|
|||
|
|
{
|
|||
|
|
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
|
|||
|
|
|
|||
|
|
int elems = 8 >> op.Size; // Size contains the target element size. (for when it becomes a doubleword)
|
|||
|
|
|
|||
|
|
Operand res = GetVecA32(op.Qd);
|
|||
|
|
int id = (op.Vd & 1) << (3 - op.Size); // Target doubleword base.
|
|||
|
|
|
|||
|
|
for (int index = 0; index < elems; index++)
|
|||
|
|
{
|
|||
|
|
Operand m = EmitVectorExtract32(context, op.Qm, index, op.Size + 1, false);
|
|||
|
|
|
|||
|
|
res = EmitVectorInsert(context, res, emit(m), id + index, op.Size);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
context.Copy(GetVecA32(op.Qd), res);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
// Generic Functions
|
|||
|
|
|
|||
|
|
public static Operand EmitSoftFloatCallDefaultFpscr(
|
|||
|
|
ArmEmitterContext context,
|
|||
|
|
_F32_F32_Bool f32,
|
|||
|
|
_F64_F64_Bool f64,
|
|||
|
|
params Operand[] callArgs)
|
|||
|
|
{
|
|||
|
|
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
|
|||
|
|
|
|||
|
|
Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
|
|||
|
|
|
|||
|
|
Array.Resize(ref callArgs, callArgs.Length + 1);
|
|||
|
|
callArgs[callArgs.Length - 1] = Const(1);
|
|||
|
|
|
|||
|
|
return context.Call(dlg, callArgs);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public static Operand EmitSoftFloatCallDefaultFpscr(
|
|||
|
|
ArmEmitterContext context,
|
|||
|
|
_F32_F32_F32_Bool f32,
|
|||
|
|
_F64_F64_F64_Bool f64,
|
|||
|
|
params Operand[] callArgs)
|
|||
|
|
{
|
|||
|
|
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
|
|||
|
|
|
|||
|
|
Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
|
|||
|
|
|
|||
|
|
Array.Resize(ref callArgs, callArgs.Length + 1);
|
|||
|
|
callArgs[callArgs.Length - 1] = Const(1);
|
|||
|
|
|
|||
|
|
return context.Call(dlg, callArgs);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public static Operand EmitSoftFloatCallDefaultFpscr(
|
|||
|
|
ArmEmitterContext context,
|
|||
|
|
_F32_F32_F32_F32_Bool f32,
|
|||
|
|
_F64_F64_F64_F64_Bool f64,
|
|||
|
|
params Operand[] callArgs)
|
|||
|
|
{
|
|||
|
|
IOpCodeSimd op = (IOpCodeSimd)context.CurrOp;
|
|||
|
|
|
|||
|
|
Delegate dlg = (op.Size & 1) == 0 ? (Delegate)f32 : (Delegate)f64;
|
|||
|
|
|
|||
|
|
Array.Resize(ref callArgs, callArgs.Length + 1);
|
|||
|
|
callArgs[callArgs.Length - 1] = Const(1);
|
|||
|
|
|
|||
|
|
return context.Call(dlg, callArgs);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public static Operand EmitVectorExtractSx32(ArmEmitterContext context, int reg, int index, int size)
|
|||
|
|
{
|
|||
|
|
return EmitVectorExtract32(context, reg, index, size, true);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public static Operand EmitVectorExtractZx32(ArmEmitterContext context, int reg, int index, int size)
|
|||
|
|
{
|
|||
|
|
return EmitVectorExtract32(context, reg, index, size, false);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
public static Operand EmitVectorExtract32(ArmEmitterContext context, int reg, int index, int size, bool signed)
|
|||
|
|
{
|
|||
|
|
ThrowIfInvalid(index, size);
|
|||
|
|
|
|||
|
|
Operand res = null;
|
|||
|
|
|
|||
|
|
switch (size)
|
|||
|
|
{
|
|||
|
|
case 0:
|
|||
|
|
res = context.VectorExtract8(GetVec(reg), index);
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case 1:
|
|||
|
|
res = context.VectorExtract16(GetVec(reg), index);
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case 2:
|
|||
|
|
res = context.VectorExtract(OperandType.I32, GetVec(reg), index);
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case 3:
|
|||
|
|
res = context.VectorExtract(OperandType.I64, GetVec(reg), index);
|
|||
|
|
break;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (signed)
|
|||
|
|
{
|
|||
|
|
switch (size)
|
|||
|
|
{
|
|||
|
|
case 0: res = context.SignExtend8(OperandType.I32, res); break;
|
|||
|
|
case 1: res = context.SignExtend16(OperandType.I32, res); break;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
switch (size)
|
|||
|
|
{
|
|||
|
|
case 0: res = context.ZeroExtend8(OperandType.I32, res); break;
|
|||
|
|
case 1: res = context.ZeroExtend16(OperandType.I32, res); break;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return res;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|