101 lines
2.4 KiB
C++
Executable File
101 lines
2.4 KiB
C++
Executable File
// SPDX-FileCopyrightText: 2021 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-3.0-or-later
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#pragma once
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#include "common/common_types.h"
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#include "common/address_space.h"
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#include "video_core/cdma_pusher.h"
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#include "video_core/host1x/gpu_device_memory_manager.h"
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#include "video_core/host1x/syncpoint_manager.h"
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#include "video_core/memory_manager.h"
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namespace Core {
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class System;
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} // namespace Core
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namespace Tegra::Host1x {
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class Nvdec;
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enum class ChannelType : u32 {
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MsEnc = 0,
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VIC = 1,
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GPU = 2,
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NvDec = 3,
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Display = 4,
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NvJpg = 5,
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TSec = 6,
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Max = 7,
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};
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class Host1x {
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public:
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explicit Host1x(Core::System& system);
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~Host1x();
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Core::System& System() {
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return system;
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}
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SyncpointManager& GetSyncpointManager() {
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return syncpoint_manager;
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}
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const SyncpointManager& GetSyncpointManager() const {
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return syncpoint_manager;
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}
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Tegra::MaxwellDeviceMemoryManager& MemoryManager() {
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return memory_manager;
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}
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const Tegra::MaxwellDeviceMemoryManager& MemoryManager() const {
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return memory_manager;
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}
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Tegra::MemoryManager& GMMU() {
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return gmmu_manager;
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}
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const Tegra::MemoryManager& GMMU() const {
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return gmmu_manager;
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}
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Common::FlatAllocator<u32, 0, 32>& Allocator() {
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return *allocator;
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}
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const Common::FlatAllocator<u32, 0, 32>& Allocator() const {
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return *allocator;
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}
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void StartDevice(s32 fd, ChannelType type, u32 syncpt);
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void StopDevice(s32 fd, ChannelType type);
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void PushEntries(s32 fd, ChCommandHeaderList&& entries) {
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auto it = devices.find(fd);
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if (it == devices.end()) {
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return;
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}
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it->second->PushEntries(std::move(entries));
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}
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Nvdec& GetLastNvdecDevice() {
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auto it = devices.find(last_nvdec_fd);
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ASSERT(it->second.get() != nullptr);
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return *reinterpret_cast<Nvdec*>(it->second.get());
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}
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private:
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Core::System& system;
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SyncpointManager syncpoint_manager;
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Tegra::MaxwellDeviceMemoryManager memory_manager;
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Tegra::MemoryManager gmmu_manager;
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std::unique_ptr<Common::FlatAllocator<u32, 0, 32>> allocator;
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std::unordered_map<s32, std::unique_ptr<CDmaPusher>> devices;
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s32 last_nvdec_fd{};
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};
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} // namespace Tegra::Host1x
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