early-access version 2173

This commit is contained in:
pineappleEA 2021-10-31 18:43:26 +01:00
parent 943e9729fe
commit b37854dccc
8 changed files with 63 additions and 4 deletions

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@ -1,7 +1,7 @@
yuzu emulator early access
=============
This is the source code for early-access 2172.
This is the source code for early-access 2173.
## Legal Notice

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@ -2,6 +2,10 @@
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
// SPDX-License-Identifier: MPL-2.0
// Copyright 2021 Skyline Team and Contributors (https://github.com/skyline-emu/)
// Copyright 2019-2020 Ryujinx Team and Contributors
#include <cstdlib>
#include <cstring>
@ -38,6 +42,8 @@ NvResult nvhost_ctrl::Ioctl1(DeviceFD fd, Ioctl command, const std::vector<u8>&
return IocCtrlEventRegister(input, output);
case 0x20:
return IocCtrlEventUnregister(input, output);
case 0x21:
return IocCtrlFreeEventBatch(input, output);
}
break;
default:
@ -212,4 +218,18 @@ NvResult nvhost_ctrl::IocCtrlClearEventWait(const std::vector<u8>& input, std::v
return NvResult::Success;
}
NvResult nvhost_ctrl::IocCtrlFreeEventBatch(const std::vector<u8>& input, std::vector<u8>& output) {
IocCtrlFreeEventBatchParams params{};
std::memcpy(&params, input.data(), sizeof(params));
LOG_DEBUG(Service_NVDRV, "called, bit_mask={}", params.bit_mask);
for (u32 event_id = 0; event_id < MaxNvEvents; ++event_id) {
if (params.bit_mask & (1ULL << event_id)) {
events_interface.UnregisterEvent(event_id);
}
}
return NvResult::Success;
}
} // namespace Service::Nvidia::Devices

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@ -119,16 +119,18 @@ private:
static_assert(sizeof(IocCtrlEventUnregisterParams) == 4,
"IocCtrlEventUnregisterParams is incorrect size");
struct IocCtrlEventKill {
u64_le user_events{};
struct IocCtrlFreeEventBatchParams {
u64_le bit_mask{};
};
static_assert(sizeof(IocCtrlEventKill) == 8, "IocCtrlEventKill is incorrect size");
static_assert(sizeof(IocCtrlFreeEventBatchParams) == 8,
"IocCtrlFreeEventBatchParams is incorrect size");
NvResult NvOsGetConfigU32(const std::vector<u8>& input, std::vector<u8>& output);
NvResult IocCtrlEventWait(const std::vector<u8>& input, std::vector<u8>& output, bool is_async);
NvResult IocCtrlEventRegister(const std::vector<u8>& input, std::vector<u8>& output);
NvResult IocCtrlEventUnregister(const std::vector<u8>& input, std::vector<u8>& output);
NvResult IocCtrlClearEventWait(const std::vector<u8>& input, std::vector<u8>& output);
NvResult IocCtrlFreeEventBatch(const std::vector<u8>& input, std::vector<u8>& output);
EventInterface& events_interface;
SyncpointManager& syncpoint_manager;

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@ -155,6 +155,17 @@ public:
return instructions.crend();
}
// Set the order of the block, it can be set pre order, the user decides
void SetOrder(u32 new_order) {
order = new_order;
}
// Get the order of the block.
// The higher, the closer is the block to the end.
[[nodiscard]] u32 GetOrder() const {
return order;
}
private:
/// Memory pool for instruction list
ObjectPool<Inst>* inst_pool;
@ -174,6 +185,9 @@ private:
/// Intrusively stored host definition of this block.
u32 definition{};
/// Order of the block.
u32 order{};
};
using BlockList = std::vector<Block*>;

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@ -6,6 +6,7 @@
#include <memory>
#include "shader_recompiler/exception.h"
#include "shader_recompiler/frontend/ir/basic_block.h"
#include "shader_recompiler/frontend/ir/type.h"
#include "shader_recompiler/frontend/ir/value.h"
@ -302,6 +303,16 @@ void Inst::AddPhiOperand(Block* predecessor, const Value& value) {
phi_args.emplace_back(predecessor, value);
}
void Inst::OrderPhiArgs() {
if (op != Opcode::Phi) {
throw LogicError("{} is not a Phi instruction", op);
}
std::sort(phi_args.begin(), phi_args.end(),
[](const std::pair<Block*, Value>& a, const std::pair<Block*, Value>& b) {
return a.first->GetOrder() < b.first->GetOrder();
});
}
void Inst::Invalidate() {
ClearArgs();
ReplaceOpcode(Opcode::Void);

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@ -182,6 +182,9 @@ public:
/// Add phi operand to a phi instruction.
void AddPhiOperand(Block* predecessor, const Value& value);
/// Orders the Phi arguments.
void OrderPhiArgs();
void Invalidate();
void ClearArgs();

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@ -27,9 +27,11 @@ IR::BlockList GenerateBlocks(const IR::AbstractSyntaxList& syntax_list) {
}
IR::BlockList blocks;
blocks.reserve(num_syntax_blocks);
u32 order_index{};
for (const auto& node : syntax_list) {
if (node.type == IR::AbstractSyntaxNode::Type::Block) {
blocks.push_back(node.data.block);
blocks.back()->SetOrder(order_index++);
}
}
return blocks;

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@ -378,6 +378,13 @@ void SsaRewritePass(IR::Program& program) {
for (auto block = program.post_order_blocks.rbegin(); block != end; ++block) {
VisitBlock(pass, *block);
}
for (auto block = program.post_order_blocks.rbegin(); block != end; ++block) {
for (IR::Inst& inst : (*block)->Instructions()) {
if (inst.GetOpcode() == IR::Opcode::Phi) {
inst.OrderPhiArgs();
}
}
}
}
} // namespace Shader::Optimization