From c430d24d2f609ae7cdfeeefaa264f938b2584474 Mon Sep 17 00:00:00 2001 From: cam900 Date: Mon, 28 Mar 2022 01:12:44 +0900 Subject: [PATCH] VRC6 has internal timer --- papers/doc/7-systems/vrc6.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/papers/doc/7-systems/vrc6.md b/papers/doc/7-systems/vrc6.md index c60ae26f6..7dfc2585f 100644 --- a/papers/doc/7-systems/vrc6.md +++ b/papers/doc/7-systems/vrc6.md @@ -6,7 +6,7 @@ The chip has 2 pulse wave channel and single sawtooth channel. volume register is 4 bit for pulse wave and 6 bit for sawtooth, but sawtooth output is corrupted when volume register value is too high. because this register is 8 bit accumulator in technically, its output is wraparoundable. pulse wave duty cycle is 8 level, it can be ignored and it has potential for DAC at this case: volume register in this mode is DAC output and it can be PCM playback through this mode. -Furnace supports this routine for PCM playback, but it's consume a lot of CPU resource in real hardware. +Furnace supports this routine for PCM playback, but it's consume a lot of CPU resource in real hardware. (even if conjunction with VRC6 integrated IRQ timer) # effects