From a19090ab9b5091db262ea9f778c33c9bad6bfb86 Mon Sep 17 00:00:00 2001
From: Laurens Holst <laurens@grauw.nl>
Date: Tue, 24 May 2022 22:08:01 +0200
Subject: [PATCH 1/2] Correct VGM chip ID for Y8950 reset.

---
 src/engine/vgmOps.cpp | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/engine/vgmOps.cpp b/src/engine/vgmOps.cpp
index 137791ac8..f11cb7b5c 100644
--- a/src/engine/vgmOps.cpp
+++ b/src/engine/vgmOps.cpp
@@ -386,22 +386,22 @@ void DivEngine::performVGMWrite(SafeWriter* w, DivSystem sys, DivRegWrite& write
       case DIV_SYSTEM_Y8950_DRUMS:
         // disable envelope
         for (int i=0; i<6; i++) {
-          w->writeC(0x0b|baseAddr1);
+          w->writeC(0x0c|baseAddr1);
           w->writeC(0x80+i);
           w->writeC(0x0f);
-          w->writeC(0x0b|baseAddr1);
+          w->writeC(0x0c|baseAddr1);
           w->writeC(0x88+i);
           w->writeC(0x0f);
-          w->writeC(0x0b|baseAddr1);
+          w->writeC(0x0c|baseAddr1);
           w->writeC(0x90+i);
           w->writeC(0x0f);
         }
         // key off + freq reset
         for (int i=0; i<9; i++) {
-          w->writeC(0x0b|baseAddr1);
+          w->writeC(0x0c|baseAddr1);
           w->writeC(0xa0+i);
           w->writeC(0);
-          w->writeC(0x0b|baseAddr1);
+          w->writeC(0x0c|baseAddr1);
           w->writeC(0xb0+i);
           w->writeC(0);
         }

From 4b4bc9841784b0c97a6920ee534d27dbc7a2a0d8 Mon Sep 17 00:00:00 2001
From: Laurens Holst <laurens@grauw.nl>
Date: Tue, 24 May 2022 22:09:36 +0200
Subject: [PATCH 2/2] Stop / reset Y8950 ADPCM before restarting.

The emulation core treats every write to register 7 with start bit set as
a retrigger. This is not how the real hardware behaves.
---
 src/engine/platform/opl.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/engine/platform/opl.cpp b/src/engine/platform/opl.cpp
index aed4c315c..c9996e296 100644
--- a/src/engine/platform/opl.cpp
+++ b/src/engine/platform/opl.cpp
@@ -735,6 +735,7 @@ int DivPlatformOPL::dispatch(DivCommand c) {
           if (chan[c.chan].sample>=0 && chan[c.chan].sample<parent->song.sampleLen) {
             DivSample* s=parent->getSample(chan[c.chan].sample);
             immWrite(8,0);
+            immWrite(7,0x01); // reset
             immWrite(9,(s->offB>>2)&0xff);
             immWrite(10,(s->offB>>10)&0xff);
             int end=s->offB+s->lengthB-1;
@@ -770,6 +771,7 @@ int DivPlatformOPL::dispatch(DivCommand c) {
           }
           DivSample* s=parent->getSample(12*sampleBank+c.value%12);
           immWrite(8,0);
+          immWrite(7,0x01); // reset
           immWrite(9,(s->offB>>2)&0xff);
           immWrite(10,(s->offB>>10)&0xff);
           int end=s->offB+s->lengthB-1;