From 7bdda990e1605f9e5ff9c95c68313b3088aabfa4 Mon Sep 17 00:00:00 2001 From: tildearrow Date: Fri, 20 Jan 2023 04:52:27 -0500 Subject: [PATCH] OPL: partially implement new hard reset it's so late --- src/engine/platform/opl.cpp | 95 ++++++++++++++++++++++++++----------- 1 file changed, 66 insertions(+), 29 deletions(-) diff --git a/src/engine/platform/opl.cpp b/src/engine/platform/opl.cpp index a60b59da..afaba9f9 100644 --- a/src/engine/platform/opl.cpp +++ b/src/engine/platform/opl.cpp @@ -446,35 +446,34 @@ void DivPlatformOPL::tick(bool sysTick) { } } } + } - if (i0x100) { + weWillWriteRRLater[(baseAddr&0xff)|32]=true; + } else { + weWillWriteRRLater[(baseAddr&0xff)]=true; } + immWrite(baseAddr+ADDR_SL_RR,0x0f); + hardResetElapsed++; } } } @@ -562,6 +561,11 @@ void DivPlatformOPL::tick(bool sysTick) { for (int i=0; i<512; i++) { if (pendingWrites[i]!=oldWrites[i]) { + if ((i>=0x80 && i<0xa0)) { + if (weWillWriteRRLater[i-0x80]) continue; + } else if ((i>=0x180 && i<0x1a0)) { + if (weWillWriteRRLater[32|(i-0x180)]) continue; + } immWrite(i,pendingWrites[i]&0xff); oldWrites[i]=pendingWrites[i]; } @@ -580,11 +584,15 @@ void DivPlatformOPL::tick(bool sysTick) { immWrite(chanMap[i]+ADDR_FREQ,chan[i].freqL); } if (i