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OPZ: fix muting

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tildearrow 2022-05-02 01:15:42 -05:00
parent 6380876b9a
commit 34f7750c27
1 changed files with 64 additions and 50 deletions
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114
src/engine/platform/tx81z.cpp
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@ -198,10 +198,14 @@ void DivPlatformTX81Z::tick(bool sysTick) {
for (int j=0; j<4; j++) { for (int j=0; j<4; j++) {
unsigned short baseAddr=chanOffs[i]|opOffs[j]; unsigned short baseAddr=chanOffs[i]|opOffs[j];
DivInstrumentFM::Operator& op=chan[i].state.op[j]; DivInstrumentFM::Operator& op=chan[i].state.op[j];
if (isOutput[chan[i].state.alg][j]) { if (isMuted[i]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].outVol&0x7f))/127)); rWrite(baseAddr+ADDR_TL,127);
} else { } else {
rWrite(baseAddr+ADDR_TL,op.tl); if (isOutput[chan[i].state.alg][j]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].outVol&0x7f))/127));
} else {
rWrite(baseAddr+ADDR_TL,op.tl);
}
} }
} }
} }
@ -266,11 +270,7 @@ void DivPlatformTX81Z::tick(bool sysTick) {
if (chan[i].std.alg.had) { if (chan[i].std.alg.had) {
chan[i].state.alg=chan[i].std.alg.val; chan[i].state.alg=chan[i].std.alg.val;
if (isMuted[i]) { immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|(chan[i].active?0:0x40)|(chan[i].chVolR<<7));
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x40);
} else {
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|(chan[i].active?0:0x40)|(chan[i].chVolR<<7));
}
if (!parent->song.algMacroBehavior) for (int j=0; j<4; j++) { if (!parent->song.algMacroBehavior) for (int j=0; j<4; j++) {
unsigned short baseAddr=chanOffs[i]|opOffs[j]; unsigned short baseAddr=chanOffs[i]|opOffs[j];
DivInstrumentFM::Operator& op=chan[i].state.op[j]; DivInstrumentFM::Operator& op=chan[i].state.op[j];
@ -287,11 +287,7 @@ void DivPlatformTX81Z::tick(bool sysTick) {
} }
if (chan[i].std.fb.had) { if (chan[i].std.fb.had) {
chan[i].state.fb=chan[i].std.fb.val; chan[i].state.fb=chan[i].std.fb.val;
if (isMuted[i]) { immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|(chan[i].active?0:0x40)|(chan[i].chVolR<<7));
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x40);
} else {
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|(chan[i].active?0:0x40)|(chan[i].chVolR<<7));
}
} }
if (chan[i].std.fms.had) { if (chan[i].std.fms.had) {
chan[i].state.fms=chan[i].std.fms.val; chan[i].state.fms=chan[i].std.fms.val;
@ -331,10 +327,14 @@ void DivPlatformTX81Z::tick(bool sysTick) {
} }
if (m.tl.had) { if (m.tl.had) {
op.tl=127-m.tl.val; op.tl=127-m.tl.val;
if (isOutput[chan[i].state.alg][j]) { if (isMuted[i]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].outVol&0x7f))/127)); rWrite(baseAddr+ADDR_TL,127);
} else { } else {
rWrite(baseAddr+ADDR_TL,op.tl); if (isOutput[chan[i].state.alg][j]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].outVol&0x7f))/127));
} else {
rWrite(baseAddr+ADDR_TL,op.tl);
}
} }
} }
if (m.rs.had) { if (m.rs.had) {
@ -364,12 +364,8 @@ void DivPlatformTX81Z::tick(bool sysTick) {
oldWrites[baseAddr+ADDR_TL]=-1; oldWrites[baseAddr+ADDR_TL]=-1;
} }
} }
if (isMuted[i]) { //if (chan[i].keyOn) immWrite(0x08,i);
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x00); immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x00|(chan[i].chVolR<<7));
} else {
//if (chan[i].keyOn) immWrite(0x08,i);
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x00|(chan[i].chVolR<<7));
}
if (chan[i].hardReset && chan[i].keyOn) { if (chan[i].hardReset && chan[i].keyOn) {
for (int j=0; j<4; j++) { for (int j=0; j<4; j++) {
unsigned short baseAddr=chanOffs[i]|opOffs[j]; unsigned short baseAddr=chanOffs[i]|opOffs[j];
@ -411,12 +407,8 @@ void DivPlatformTX81Z::tick(bool sysTick) {
chan[i].freqChanged=false; chan[i].freqChanged=false;
} }
if (chan[i].keyOn) { if (chan[i].keyOn) {
if (isMuted[i]) { //immWrite(0x08,i);
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)); immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x40|(chan[i].chVolR<<7));
} else {
//immWrite(0x08,i);
immWrite(chanOffs[i]+ADDR_LR_FB_ALG,(chan[i].state.alg&7)|(chan[i].state.fb<<3)|0x40|(chan[i].chVolR<<7));
}
chan[i].keyOn=false; chan[i].keyOn=false;
} }
} }
@ -424,13 +416,19 @@ void DivPlatformTX81Z::tick(bool sysTick) {
void DivPlatformTX81Z::muteChannel(int ch, bool mute) { void DivPlatformTX81Z::muteChannel(int ch, bool mute) {
isMuted[ch]=mute; isMuted[ch]=mute;
// TODO: use volume registers! for (int i=0; i<4; i++) {
/* unsigned short baseAddr=chanOffs[ch]|opOffs[i];
if (isMuted[ch]) { DivInstrumentFM::Operator op=chan[ch].state.op[i];
immWrite(chanOffs[ch]+ADDR_LR_FB_ALG,(chan[ch].state.alg&7)|(chan[ch].state.fb<<3)); if (isMuted[ch]) {
} else { rWrite(baseAddr+ADDR_TL,127);
immWrite(chanOffs[ch]+ADDR_LR_FB_ALG,(chan[ch].state.alg&7)|(chan[ch].state.fb<<3)|((chan[ch].chVolL&1)<<6)|((chan[ch].chVolR&1)<<7)); } else {
}*/ if (isOutput[chan[ch].state.alg][i]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[ch].outVol&0x7f))/127));
} else {
rWrite(baseAddr+ADDR_TL,op.tl);
}
}
}
} }
int DivPlatformTX81Z::dispatch(DivCommand c) { int DivPlatformTX81Z::dispatch(DivCommand c) {
@ -450,13 +448,17 @@ int DivPlatformTX81Z::dispatch(DivCommand c) {
for (int i=0; i<4; i++) { for (int i=0; i<4; i++) {
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i]; unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
DivInstrumentFM::Operator op=chan[c.chan].state.op[i]; DivInstrumentFM::Operator op=chan[c.chan].state.op[i];
if (isOutput[chan[c.chan].state.alg][i]) { if (isMuted[c.chan]) {
if (!chan[c.chan].active || chan[c.chan].insChanged) { rWrite(baseAddr+ADDR_TL,127);
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[c.chan].outVol&0x7f))/127));
}
} else { } else {
if (chan[c.chan].insChanged) { if (isOutput[chan[c.chan].state.alg][i]) {
rWrite(baseAddr+ADDR_TL,op.tl); if (!chan[c.chan].active || chan[c.chan].insChanged) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[c.chan].outVol&0x7f))/127));
}
} else {
if (chan[c.chan].insChanged) {
rWrite(baseAddr+ADDR_TL,op.tl);
}
} }
} }
if (chan[c.chan].insChanged) { if (chan[c.chan].insChanged) {
@ -512,10 +514,14 @@ int DivPlatformTX81Z::dispatch(DivCommand c) {
for (int i=0; i<4; i++) { for (int i=0; i<4; i++) {
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i]; unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i]; DivInstrumentFM::Operator& op=chan[c.chan].state.op[i];
if (isOutput[chan[c.chan].state.alg][i]) { if (isMuted[c.chan]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[c.chan].outVol&0x7f))/127)); rWrite(baseAddr+ADDR_TL,127);
} else { } else {
rWrite(baseAddr+ADDR_TL,op.tl); if (isOutput[chan[c.chan].state.alg][i]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[c.chan].outVol&0x7f))/127));
} else {
rWrite(baseAddr+ADDR_TL,op.tl);
}
} }
} }
break; break;
@ -606,10 +612,14 @@ int DivPlatformTX81Z::dispatch(DivCommand c) {
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]]; unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]];
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]]; DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]];
op.tl=c.value2; op.tl=c.value2;
if (isOutput[chan[c.chan].state.alg][c.value]) { if (isMuted[c.chan]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[c.chan].outVol&0x7f))/127)); rWrite(baseAddr+ADDR_TL,127);
} else { } else {
rWrite(baseAddr+ADDR_TL,op.tl); if (isOutput[chan[c.chan].state.alg][c.value]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[c.chan].outVol&0x7f))/127));
} else {
rWrite(baseAddr+ADDR_TL,op.tl);
}
} }
break; break;
} }
@ -678,10 +688,14 @@ void DivPlatformTX81Z::forceIns() {
for (int j=0; j<4; j++) { for (int j=0; j<4; j++) {
unsigned short baseAddr=chanOffs[i]|opOffs[j]; unsigned short baseAddr=chanOffs[i]|opOffs[j];
DivInstrumentFM::Operator op=chan[i].state.op[j]; DivInstrumentFM::Operator op=chan[i].state.op[j];
if (isOutput[chan[i].state.alg][j]) { if (isMuted[i]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].outVol&0x7f))/127)); rWrite(baseAddr+ADDR_TL,127);
} else { } else {
rWrite(baseAddr+ADDR_TL,op.tl); if (isOutput[chan[i].state.alg][j]) {
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[i].outVol&0x7f))/127));
} else {
rWrite(baseAddr+ADDR_TL,op.tl);
}
} }
rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4)); rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4));
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.egt<<5)|(op.rs<<6)); rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.egt<<5)|(op.rs<<6));