From 1bcdedda3ef524a9c721743f81747b5c2386fea9 Mon Sep 17 00:00:00 2001 From: tildearrow Date: Wed, 22 Nov 2023 16:35:02 -0500 Subject: [PATCH] prepare the addition of more OPL emulation cores --- CMakeLists.txt | 2 + extern/YM3812-LLE/LICENSE | 339 +++ extern/YM3812-LLE/Readme.md | 13 + extern/YM3812-LLE/fmopl2.c | 1501 +++++++++++++ extern/YM3812-LLE/fmopl2.h | 272 +++ extern/YMF262-LLE/LICENSE | 339 +++ extern/YMF262-LLE/Readme.md | 13 + extern/YMF262-LLE/fmopl3.c | 1646 ++++++++++++++ extern/YMF262-LLE/fmopl3.h | 333 +++ src/engine/platform/sound/ymfm/ymfm_opl.cpp | 2139 +++++++++++++++++++ src/engine/platform/sound/ymfm/ymfm_opl.h | 902 ++++++++ src/engine/platform/sound/ymfm/ymfm_pcm.cpp | 714 +++++++ src/engine/platform/sound/ymfm/ymfm_pcm.h | 347 +++ 13 files changed, 8560 insertions(+) create mode 100644 extern/YM3812-LLE/LICENSE create mode 100644 extern/YM3812-LLE/Readme.md create mode 100644 extern/YM3812-LLE/fmopl2.c create mode 100644 extern/YM3812-LLE/fmopl2.h create mode 100644 extern/YMF262-LLE/LICENSE create mode 100644 extern/YMF262-LLE/Readme.md create mode 100644 extern/YMF262-LLE/fmopl3.c create mode 100644 extern/YMF262-LLE/fmopl3.h create mode 100644 src/engine/platform/sound/ymfm/ymfm_opl.cpp create mode 100644 src/engine/platform/sound/ymfm/ymfm_opl.h create mode 100644 src/engine/platform/sound/ymfm/ymfm_pcm.cpp create mode 100644 src/engine/platform/sound/ymfm/ymfm_pcm.h diff --git a/CMakeLists.txt b/CMakeLists.txt index d50f19328..e0bbe826c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -556,9 +556,11 @@ src/engine/platform/sound/tia/AudioChannel.cpp src/engine/platform/sound/tia/Audio.cpp src/engine/platform/sound/ymfm/ymfm_adpcm.cpp +src/engine/platform/sound/ymfm/ymfm_opl.cpp src/engine/platform/sound/ymfm/ymfm_opm.cpp src/engine/platform/sound/ymfm/ymfm_opn.cpp src/engine/platform/sound/ymfm/ymfm_opz.cpp +src/engine/platform/sound/ymfm/ymfm_pcm.cpp src/engine/platform/sound/ymfm/ymfm_ssg.cpp src/engine/platform/sound/lynx/Mikey.cpp diff --git a/extern/YM3812-LLE/LICENSE b/extern/YM3812-LLE/LICENSE new file mode 100644 index 000000000..89e08fb00 --- /dev/null +++ b/extern/YM3812-LLE/LICENSE @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. And you must show them these terms so they know their +rights. + + We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. (Exception: if the Program itself is interactive but + does not normally print such an announcement, your work based on + the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Program, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. (This alternative is + allowed only for noncommercial distribution and only if you + received the program in object code or executable form with such + an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for +making modifications to it. For an executable work, complete source +code means all the source code for all modules it contains, plus any +associated interface definition files, plus the scripts used to +control compilation and installation of the executable. However, as a +special exception, the source code distributed need not include +anything that is normally distributed (in either source or binary +form) with the major components (compiler, kernel, and so on) of the +operating system on which the executable runs, unless that component +itself accompanies the executable. + +If distribution of executable or object code is made by offering +access to copy from a designated place, then offering equivalent +access to copy the source code from the same place counts as +distribution of the source code, even though third parties are not +compelled to copy the source along with the object code. + + 4. You may not copy, modify, sublicense, or distribute the Program +except as expressly provided under this License. Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + + 5. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + + 6. Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 7. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. For example, if a patent +license would not permit royalty-free redistribution of the Program by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under +any particular circumstance, the balance of the section is intended to +apply and the section as a whole is intended to apply in other +circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system, which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 8. If the distribution and/or use of the Program is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Program under this License +may add an explicit geographical distribution limitation excluding +those countries, so that distribution is permitted only in or among +countries not thus excluded. In such case, this License incorporates +the limitation as if written in the body of this License. + + 9. The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/extern/YM3812-LLE/Readme.md b/extern/YM3812-LLE/Readme.md new file mode 100644 index 000000000..38aa0debb --- /dev/null +++ b/extern/YM3812-LLE/Readme.md @@ -0,0 +1,13 @@ +# YM3812-LLE + +Yamaha YM3812 (OPL2) emulator using YM3812 die shot. + +Special thanks to Travis Goodspeed for decapping YM3812. + +https://twitter.com/travisgoodspeed/status/1652334901230723072 + +# MODIFICATION DISCLAIMER + +this is a modified version of YM3812-LLE which adds functions to allow its usage. + +the original Git commit is 7f0c6537ccd61e9e7dbddb4e4a353e007ea69c50. diff --git a/extern/YM3812-LLE/fmopl2.c b/extern/YM3812-LLE/fmopl2.c new file mode 100644 index 000000000..a1a08f5c5 --- /dev/null +++ b/extern/YM3812-LLE/fmopl2.c @@ -0,0 +1,1501 @@ +/* + * Copyright (C) 2023 nukeykt + * + * This file is part of YM3812-LLE. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * YM3812 emulator + * Thanks: + * Travis Goodspeed: + * YM3812 decap and die shot + * + */ + +#include "fmopl2.h" + + +void FMOPL2_DoShiftRegisters(fmopl2_t *chip, int sel) +{ + int j; + int to = sel; + int from = sel ^ 1; + int rot = sel == 0 ? 1 : 0; +#define CH_ROTATE(x) rot ? ((x << 1) | ((x >> 8) & 1)) : x +#define OP_ROTATE(x) rot ? ((x << 1) | ((x >> 17) & 1)) : x + // channel registers + + // fnum + for (j = 0; j < 10; j++) + chip->ch_fnum[j][to] = CH_ROTATE(chip->ch_fnum[j][from]); + // block + for (j = 0; j < 3; j++) + chip->ch_block[j][to] = CH_ROTATE(chip->ch_block[j][from]); + // kon + chip->ch_keyon[to] = CH_ROTATE(chip->ch_keyon[from]); + // connect + chip->ch_connect[to] = CH_ROTATE(chip->ch_connect[from]); + // feedback + for (j = 0; j < 3; j++) + chip->ch_fb[j][to] = CH_ROTATE(chip->ch_fb[j][from]); + // multi + for (j = 0; j < 4; j++) + chip->op_multi[j][to] = OP_ROTATE(chip->op_multi[j][from]); + // ksr + chip->op_ksr[to] = OP_ROTATE(chip->op_ksr[from]); + // egt + chip->op_egt[to] = OP_ROTATE(chip->op_egt[from]); + // vib + chip->op_vib[to] = OP_ROTATE(chip->op_vib[from]); + // am + chip->op_am[to] = OP_ROTATE(chip->op_am[from]); + // tl + for (j = 0; j < 6; j++) + chip->op_tl[j][to] = OP_ROTATE(chip->op_tl[j][from]); + // ksl + for (j = 0; j < 2; j++) + chip->op_ksl[j][to] = OP_ROTATE(chip->op_ksl[j][from]); + // ar + for (j = 0; j < 4; j++) + chip->op_ar[j][to] = OP_ROTATE(chip->op_ar[j][from]); + // dr + for (j = 0; j < 4; j++) + chip->op_dr[j][to] = OP_ROTATE(chip->op_dr[j][from]); + // sl + for (j = 0; j < 4; j++) + chip->op_sl[j][to] = OP_ROTATE(chip->op_sl[j][from]); + // rr + for (j = 0; j < 4; j++) + chip->op_rr[j][to] = OP_ROTATE(chip->op_rr[j][from]); + // wf + for (j = 0; j < 2; j++) + chip->op_wf[j][to] = OP_ROTATE(chip->op_wf[j][from]); +#undef CH_ROTATE +#undef OP_ROTATE +} + +enum { + eg_state_attack = 0, + eg_state_decay, + eg_state_sustain, + eg_state_release +}; + +void FMOPL2_Clock(fmopl2_t *chip) +{ + int i; + + chip->mclk1 = !chip->input.mclk; + chip->mclk2 = chip->input.mclk; + + chip->reset1 = !chip->input.ic; + chip->io_rd = !chip->input.rd; + chip->io_wr = !chip->input.wr; + chip->io_cs = !chip->input.cs; + chip->io_a0 = chip->input.address & 1; + + if (chip->mclk1) + { + int prescaler_reset = !(chip->prescaler_reset_l[1] & 2) && chip->reset1; + chip->prescaler_reset_l[0] = (chip->prescaler_reset_l[1] << 1) | chip->reset1; + if (prescaler_reset) + chip->prescaler_cnt[0] = 0; + else + chip->prescaler_cnt[0] = (chip->prescaler_cnt[1] + 1) & 3; + + chip->prescaler_l1[0] = !prescaler_reset && chip->prescaler_cnt[1] == 1; + chip->prescaler_l2[0] = chip->prescaler_cnt[1] == 3; + } + if (chip->mclk2) + { + chip->prescaler_reset_l[1] = chip->prescaler_reset_l[0]; + chip->prescaler_cnt[1] = chip->prescaler_cnt[0]; + chip->prescaler_l1[1] = chip->prescaler_l1[0]; + chip->prescaler_l2[1] = chip->prescaler_l2[0]; + } + + chip->clk1 = chip->prescaler_l1[1]; + chip->clk2 = chip->prescaler_l2[1]; + + chip->io_read0 = !chip->reset1 && chip->io_cs && chip->io_rd && !chip->io_a0; + chip->io_read1 = !chip->reset1 && chip->io_cs && chip->io_rd && chip->io_a0; + chip->io_write = !chip->reset1 && chip->io_cs && chip->io_wr; + chip->io_write0 = !chip->reset1 && chip->io_cs && chip->io_wr && !chip->io_a0; + chip->io_write1 = !chip->reset1 && chip->io_cs && chip->io_wr && chip->io_a0; + chip->io_dir = chip->io_cs && chip->io_rd; + + int irq = chip->t1_status || chip->t2_status || chip->unk_status1 || chip->unk_status2; + + if (!chip->io_dir) + chip->io_data = chip->input.data_i; + + if (chip->io_write) + chip->data_latch = chip->io_data; + + if (chip->write0) + chip->write0_sr = 0; + else if (chip->io_write0) + chip->write0_sr = 1; + + if (chip->write1) + chip->write1_sr = 0; + else if (chip->io_write1) + chip->write1_sr = 1; + + if (chip->mclk1) + { + chip->write0_latch[1] = chip->write0_latch[0]; + chip->write1_latch[1] = chip->write1_latch[0]; + } + if (chip->mclk2) + { + chip->write0_latch[0] = chip->write0_sr; + chip->write0_latch[2] = chip->write0_latch[1]; + + chip->write1_latch[0] = chip->write1_sr; + chip->write1_latch[2] = chip->write1_latch[1]; + } + + if (chip->clk1) + { + chip->write0_latch[4] = chip->write0_latch[3]; + chip->write1_latch[4] = chip->write1_latch[3]; + } + if (chip->clk2) + { + chip->write0_latch[3] = chip->write0_latch[2]; + chip->write0_latch[5] = chip->write0_latch[4]; + + chip->write1_latch[3] = chip->write1_latch[2]; + chip->write1_latch[5] = chip->write1_latch[4]; + } + + chip->write0 = chip->write0_latch[5]; + chip->write1 = chip->write1_latch[5]; + + //// + + if (chip->o_clk1 == chip->clk1 && chip->o_clk2 == chip->clk2 && chip->o_reset1 == chip->reset1 + && chip->o_write0 == chip->write0 && chip->o_write1 == chip->write1 && chip->o_data_latch == chip->data_latch) + goto end; // opt + + chip->o_clk1 = chip->clk1; + chip->o_clk2 = chip->clk2; + chip->o_reset1 = chip->reset1; + chip->o_write0 = chip->write0; + chip->o_write1 = chip->write1; + chip->o_data_latch = chip->data_latch; + + if (chip->write0) + { + chip->reg_sel1 = chip->data_latch == 1; + chip->reg_sel2 = chip->data_latch == 2; + chip->reg_sel3 = chip->data_latch == 3; + chip->reg_sel4 = chip->data_latch == 4; + chip->reg_sel8 = chip->data_latch == 8; + chip->reg_selbd = chip->data_latch == 0xbd; + } + + chip->reg_sel4_wr = chip->write1 && chip->reg_sel4 && (chip->data_latch & 128) == 0; + chip->reg_sel4_rst = (chip->write1 && chip->reg_sel4 && (chip->data_latch & 128) != 0) || chip->reset1; + + if (chip->reset1) + { + chip->reg_test = 0; + chip->reg_timer1 = 0; + chip->reg_timer2 = 0; + chip->reg_notesel = 0; + chip->reg_csm = 0; + chip->rhythm = 0; + chip->reg_rh_kon = 0; + chip->reg_da = 0; + chip->reg_dv = 0; + } + else if (chip->write1) + { + if (chip->reg_sel1) + chip->reg_test = chip->data_latch & 255; + if (chip->reg_sel2) + chip->reg_timer1 = chip->data_latch & 255; + if (chip->reg_sel3) + chip->reg_timer2 = chip->data_latch & 255; + if (chip->reg_sel8) + { + chip->reg_notesel = (chip->data_latch & 64) != 0; + chip->reg_csm = (chip->data_latch & 128) != 0; + } + if (chip->reg_selbd) + { + chip->reg_rh_kon = chip->data_latch & 31; + chip->rhythm = (chip->data_latch & 32) != 0; + chip->reg_dv = (chip->data_latch & 64) != 0; + chip->reg_da = (chip->data_latch & 128) != 0; + } + } + + if (chip->reset1) + { + chip->reg_t1_mask = 0; + chip->reg_t2_mask = 0; + chip->reg_t1_start = 0; + chip->reg_t2_start = 0; + chip->reg_mode_b3 = 0; + chip->reg_mode_b4 = 0; + } + else if (chip->reg_sel4_wr) + { + chip->reg_t1_mask = (chip->data_latch & 64) != 0; + chip->reg_t2_mask = (chip->data_latch & 32) != 0; + chip->reg_t1_start = (chip->data_latch & 1) != 0; + chip->reg_t2_start = (chip->data_latch & 2) != 0; + chip->reg_mode_b3 = (chip->data_latch & 8) != 0; + chip->reg_mode_b4 = (chip->data_latch & 16) != 0; + } + + { + chip->fsm_reset = !(chip->fsm_reset_l[1] & 2) && chip->reset1; + chip->fsm_cnt1_of = (chip->fsm_cnt1[1] & 5) == 5; + chip->fsm_cnt2_of = chip->fsm_cnt1_of && (chip->fsm_cnt2[1] & 2) != 0; + + chip->fsm_cnt = (chip->fsm_cnt2[1] << 3) | chip->fsm_cnt1[1]; + + chip->fsm_sel[0] = chip->fsm_cnt == 20 && chip->rhythm; + chip->fsm_sel[1] = chip->fsm_cnt == 19 && chip->rhythm; + chip->fsm_sel[2] = chip->fsm_cnt == 18 && chip->rhythm; + chip->fsm_sel[3] = chip->fsm_cnt == 17 && chip->rhythm; + chip->fsm_sel[4] = chip->fsm_cnt == 16 && chip->rhythm; + chip->fsm_sel[5] = chip->fsm_cnt == 20 && chip->rhythm; + chip->fsm_sel[6] = chip->fsm_cnt == 19 && chip->rhythm; + chip->fsm_sel[7] = (chip->fsm_cnt & 5) == 4; + chip->fsm_sel[8] = chip->fsm_cnt == 16; + chip->fsm_sel[9] = (chip->fsm_cnt & 29) == 5; + chip->fsm_sel[10] = chip->fsm_cnt == 16; + chip->fsm_sel[11] = chip->fsm_cnt == 11; + chip->fsm_sel[12] = chip->fsm_cnt == 20; + + int fsm_mc = !(chip->fsm_sel[7] || (chip->fsm_cnt & 2) != 0); + + chip->fsm_out[0] = ((chip->connect_l[1] & 2) != 0 || chip->fsm_sel[0] || chip->fsm_sel[1] || fsm_mc) && !chip->fsm_sel[2]; + + chip->fsm_out[1] = fsm_mc && !chip->fsm_sel[3] && !chip->fsm_sel[4]; + + chip->fsm_out[2] = !fsm_mc && !chip->fsm_sel[5] && !chip->fsm_sel[6]; + + chip->fsm_out[3] = !(chip->fsm_l1[1] && 1); + + chip->fsm_out[4] = chip->fsm_l2[1]; + + chip->fsm_out[5] = chip->fsm_sel[10]; + + chip->fsm_out[6] = chip->fsm_sel[11]; + + chip->fsm_out[7] = chip->fsm_sel[12]; + + chip->fsm_out[8] = (chip->fsm_l3[1] & 1) != 0; + + chip->fsm_out[9] = (chip->fsm_l3[1] & 2) != 0; + + chip->fsm_out[10] = (chip->fsm_l3[1] & 2) != 0; + + chip->fsm_out[11] = (chip->fsm_l4[1] & 2) != 0 && chip->rhythm; + + chip->fsm_out[12] = (chip->fsm_l5[1] & 4) != 0; + + chip->fsm_out[13] = (chip->fsm_l6[1] & 4) != 0; + + chip->fsm_out[14] = !(chip->fsm_out[12] || (chip->fsm_cnt & 16) != 0); + + chip->fsm_out[15] = !(chip->fsm_out[12] || chip->fsm_out[13]); + } + + if (chip->clk1) + { + if (chip->fsm_reset || chip->fsm_cnt1_of) + chip->fsm_cnt1[0] = 0; + else + chip->fsm_cnt1[0] = (chip->fsm_cnt1[1] + 1) & 7; + if (chip->fsm_reset || chip->fsm_cnt2_of) + chip->fsm_cnt2[0] = 0; + else + chip->fsm_cnt2[0] = (chip->fsm_cnt2[1] + chip->fsm_cnt1_of) & 3; + + chip->fsm_reset_l[0] = (chip->fsm_reset_l[1] << 1) | chip->reset1; + + chip->fsm_l1[0] = !chip->fsm_sel[8] && !chip->fsm_sel[9] && (chip->fsm_cnt & 8) == 0; + + chip->fsm_l2[0] = chip->fsm_sel[10]; + + chip->fsm_l3[0] = (chip->fsm_l3[1] << 1) | chip->fsm_sel[12]; + + chip->fsm_l4[0] = (chip->fsm_l4[1] << 1) | ((chip->fsm_cnt & 16) != 0); + + chip->fsm_l5[0] = (chip->fsm_l5[1] << 1) | ((chip->fsm_cnt & 8) != 0); + + chip->fsm_l6[0] = (chip->fsm_l6[1] << 1) | ((chip->fsm_cnt & 16) != 0); + } + if (chip->clk2) + { + chip->fsm_cnt1[1] = chip->fsm_cnt1[0]; + chip->fsm_cnt2[1] = chip->fsm_cnt2[0]; + chip->fsm_reset_l[1] = chip->fsm_reset_l[0]; + chip->fsm_l1[1] = chip->fsm_l1[0]; + chip->fsm_l2[1] = chip->fsm_l2[0]; + chip->fsm_l3[1] = chip->fsm_l3[0]; + chip->fsm_l4[1] = chip->fsm_l4[0]; + chip->fsm_l5[1] = chip->fsm_l5[0]; + chip->fsm_l6[1] = chip->fsm_l6[0]; + } + + if (chip->clk1) + chip->timer_st_load_l = chip->fsm_out[8]; + chip->timer_st_load = chip->fsm_out[8] && !chip->timer_st_load_l; + + if (chip->timer_st_load) + chip->t1_start = chip->reg_t1_start; + + if (chip->clk1) + { + int lfo = chip->lfo_cnt[1]; + int add = chip->fsm_out[8]; + + chip->lfo_cnt[0] = (chip->reg_test & 128) != 0 ? 0 : (lfo + add) & 1023; + chip->vib_cnt[0] = (chip->reg_test & 128) != 0 ? 0 : (chip->vib_cnt[1] + chip->vib_step) & 7; + } + if (chip->clk2) + { + chip->lfo_cnt[1] = chip->lfo_cnt[0]; + chip->vib_cnt[1] = chip->vib_cnt[0]; + } + + { + int lfo = chip->lfo_cnt[1]; + int add = chip->fsm_out[8]; + + chip->t1_step = (((lfo & 3) + add) & 4) != 0; + chip->t2_step = (((lfo & 15) + add) & 16) != 0; + chip->am_step = (((lfo & 63) + add) & 64) != 0; + chip->vib_step = (((lfo & 1023) + add) & 1024) != 0; + chip->vib_step |= (chip->reg_test & 8) != 0 && add; + } + + if (chip->clk1) + { + int value = chip->t1_load ? chip->reg_timer1 : chip->t1_cnt[1]; + value += ((chip->t1_start_l[1] & 1) != 0 && chip->t1_step) || (chip->reg_test & 2) != 0; + chip->t1_of[0] = (value & 256) != 0; + chip->t1_cnt[0] = (chip->t1_start_l[1] & 1) == 0 ? 0 : (value & 255); + + value = (chip->t2_of[1] || (chip->t2_start_l[1] & 3) == 1) ? chip->reg_timer2 : chip->t2_cnt[1]; + value += ((chip->t2_start_l[1] & 1) != 0 && chip->t2_step) || (chip->reg_test & 2) != 0; + chip->t2_of[0] = (value & 256) != 0; + chip->t2_cnt[0] = (chip->t2_start_l[1] & 1) == 0 ? 0 : (value & 255); + + chip->t1_start_l[0] = (chip->t1_start_l[1] << 1) | chip->t1_start; + chip->t2_start_l[0] = (chip->t2_start_l[1] << 1) | chip->reg_t2_start; + } + if (chip->clk2) + { + chip->t1_cnt[1] = chip->t1_cnt[0]; + chip->t1_of[1] = chip->t1_of[0]; + chip->t2_cnt[1] = chip->t2_cnt[0]; + chip->t2_of[1] = chip->t2_of[0]; + + chip->t1_start_l[1] = chip->t1_start_l[0]; + chip->t2_start_l[1] = chip->t2_start_l[0]; + + chip->t1_load = (chip->t1_of[1] || (chip->t1_start_l[1] & 3) == 1); // opt + } + + if (chip->reg_sel4_rst || chip->reg_t1_mask) + chip->t1_status = 0; + else if (chip->t1_of[1]) + chip->t1_status = 1; + + if (chip->reg_sel4_rst || chip->reg_t2_mask) + chip->t2_status = 0; + else if (chip->t2_of[1]) + chip->t2_status = 1; + + if (chip->reg_sel4_rst || chip->reg_mode_b4) + chip->unk_status1 = 0; + else if (0) + chip->unk_status1 = 1; + + chip->unk_status2 = 0; + + if (chip->clk1) + chip->csm_load_l = chip->fsm_out[10]; + chip->csm_load = chip->fsm_out[10] && !chip->csm_load_l; + + if (chip->csm_load) + chip->csm_kon = chip->reg_csm && chip->t1_load; + + chip->rh_sel0 = chip->rhythm && chip->fsm_out[5]; + + if (chip->clk1) + { + chip->rh_sel[0] = (chip->rh_sel[1] << 1) | chip->rh_sel0; + } + if (chip->clk2) + { + chip->rh_sel[1] = chip->rh_sel[0]; + } + + //if (chip->clk1) // opt + { + chip->keyon_comb = chip->keyon || chip->csm_kon + || (chip->rh_sel0 && (chip->reg_rh_kon & 16) != 0) // bd0 + || ((chip->rh_sel[1] & 1) != 0 && (chip->reg_rh_kon & 1) != 0) // hh + || ((chip->rh_sel[1] & 2) != 0 && (chip->reg_rh_kon & 4) != 0) // tom + || ((chip->rh_sel[1] & 4) != 0 && (chip->reg_rh_kon & 16) != 0) // bd1 + || ((chip->rh_sel[1] & 8) != 0 && (chip->reg_rh_kon & 8) != 0) // sd + || ((chip->rh_sel[1] & 16) != 0 && (chip->reg_rh_kon & 2) != 0); // tc + } + + if (chip->reset1) + chip->address = 0; + else if ((chip->data_latch & 0xe0) != 0 && chip->write0) + chip->address = chip->data_latch; + + if (chip->write0) + chip->address_valid = (chip->data_latch & 0xe0) != 0; + + if (chip->reset1) + chip->data = 0; + else if (chip->address_valid && chip->write1) + chip->data = chip->data_latch; + + chip->address_valid2 = chip->address_valid_l[1] && !chip->write0; + + if (chip->clk1) + { + chip->address_valid_l[0] = (chip->address_valid && chip->write1) || chip->address_valid2; + + int slot_cnt1_of = (chip->slot_cnt1[1] & 5) == 5; + + if (chip->fsm_out[8] || slot_cnt1_of) + chip->slot_cnt1[0] = 0; + else + chip->slot_cnt1[0] = (chip->slot_cnt1[1] + 1) & 7; + + if (chip->fsm_out[8] || (slot_cnt1_of && (chip->slot_cnt2[1] & 2) != 0)) + chip->slot_cnt2[0] = 0; + else + chip->slot_cnt2[0] = (chip->slot_cnt2[1] + slot_cnt1_of) & 3; + } + if (chip->clk2) + { + chip->address_valid_l[1] = chip->address_valid_l[0]; + + chip->slot_cnt1[1] = chip->slot_cnt1[0]; + chip->slot_cnt2[1] = chip->slot_cnt2[0]; + + chip->slot_cnt = (chip->slot_cnt2[1] << 3) | chip->slot_cnt1[1]; // opt + } + + if (chip->clk1) + { + int sel_ch = (chip->address & 0xf0) == 0xa0 || (chip->address & 0xf0) == 0xb0 || (chip->address & 0xf0) == 0xc0; + int addr_add = sel_ch && ((chip->address & 8) != 0 || (chip->address & 6) == 6); + + int addr_sel = chip->address & 1; + + addr_sel |= (((chip->address >> 1) + addr_add) & 7) << 1; + + if (!sel_ch) + addr_sel |= chip->address & 16; + + int addr_match = addr_sel == chip->slot_cnt && chip->address_valid2; + + int sel_20 = (chip->address & 0xe0) == 0x20 && addr_match; + int sel_40 = (chip->address & 0xe0) == 0x40 && addr_match; + int sel_60 = (chip->address & 0xe0) == 0x60 && addr_match; + int sel_80 = (chip->address & 0xe0) == 0x80 && addr_match; + int sel_e0 = (chip->address & 0xe0) == 0xe0 && addr_match && (chip->reg_test & 32) != 0; + + int sel_a0 = (chip->address & 0xf0) == 0xa0 && addr_match; + int sel_b0 = (chip->address & 0xf0) == 0xb0 && addr_match; + int sel_c0 = (chip->address & 0xf0) == 0xc0 && addr_match; + + FMOPL2_DoShiftRegisters(chip, 0); + + if (chip->reset1) + { + for (i = 0; i < 10; i++) + chip->ch_fnum[i][0] &= ~1; + for (i = 0; i < 3; i++) + chip->ch_block[i][0] &= ~1; + chip->ch_keyon[0] &= ~1; + chip->ch_connect[0] &= ~1; + for (i = 0; i < 3; i++) + chip->ch_fb[i][0] &= ~1; + + for (i = 0; i < 4; i++) + chip->op_multi[i][0] &= ~1; + chip->op_ksr[0] &= ~1; + chip->op_egt[0] &= ~1; + chip->op_vib[0] &= ~1; + chip->op_am[0] &= ~1; + for (i = 0; i < 6; i++) + chip->op_tl[i][0] &= ~1; + for (i = 0; i < 2; i++) + chip->op_ksl[i][0] &= ~1; + for (i = 0; i < 4; i++) + chip->op_ar[i][0] &= ~1; + for (i = 0; i < 4; i++) + chip->op_dr[i][0] &= ~1; + for (i = 0; i < 4; i++) + chip->op_sl[i][0] &= ~1; + for (i = 0; i < 4; i++) + chip->op_rr[i][0] &= ~1; + for (i = 0; i < 2; i++) + chip->op_wf[i][0] &= ~1; + } + else + { + if (sel_a0) + { + for (i = 0; i < 8; i++) + chip->ch_fnum[i][0] &= ~1; + + for (i = 0; i < 8; i++) + chip->ch_fnum[i][0] |= (chip->data >> i) & 1; + } + if (sel_b0) + { + for (i = 8; i < 10; i++) + chip->ch_fnum[i][0] &= ~1; + for (i = 0; i < 3; i++) + chip->ch_block[i][0] &= ~1; + chip->ch_keyon[0] &= ~1; + + for (i = 8; i < 10; i++) + chip->ch_fnum[i][0] |= (chip->data >> (i - 8)) & 1; + for (i = 0; i < 3; i++) + chip->ch_block[i][0] |= (chip->data >> (i + 2)) & 1; + chip->ch_keyon[0] |= (chip->data >> 5) & 1; + } + if (sel_c0) + { + chip->ch_connect[0] &= ~1; + for (i = 0; i < 3; i++) + chip->ch_fb[i][0] &= ~1; + + chip->ch_connect[0] |= (chip->data >> 0) & 1; + for (i = 0; i < 3; i++) + chip->ch_fb[i][0] |= (chip->data >> (i + 1)) & 1; + } + if (sel_20) + { + for (i = 0; i < 4; i++) + chip->op_multi[i][0] &= ~1; + chip->op_ksr[0] &= ~1; + chip->op_egt[0] &= ~1; + chip->op_vib[0] &= ~1; + chip->op_am[0] &= ~1; + + for (i = 0; i < 4; i++) + chip->op_multi[i][0] |= (chip->data >> i) & 1; + chip->op_ksr[0] |= (chip->data >> 4) & 1; + chip->op_egt[0] |= (chip->data >> 5) & 1; + chip->op_vib[0] |= (chip->data >> 6) & 1; + chip->op_am[0] |= (chip->data >> 7) & 1; + } + if (sel_40) + { + for (i = 0; i < 6; i++) + chip->op_tl[i][0] &= ~1; + for (i = 0; i < 2; i++) + chip->op_ksl[i][0] &= ~1; + + for (i = 0; i < 6; i++) + chip->op_tl[i][0] |= (chip->data >> i) & 1; + for (i = 0; i < 2; i++) + chip->op_ksl[i][0] |= (chip->data >> (i + 6)) & 1; + } + if (sel_60) + { + for (i = 0; i < 4; i++) + chip->op_ar[i][0] &= ~1; + for (i = 0; i < 4; i++) + chip->op_dr[i][0] &= ~1; + + for (i = 0; i < 4; i++) + chip->op_ar[i][0] |= (chip->data >> (i + 4)) & 1; + for (i = 0; i < 4; i++) + chip->op_dr[i][0] |= (chip->data >> i) & 1; + } + if (sel_80) + { + for (i = 0; i < 4; i++) + chip->op_sl[i][0] &= ~1; + for (i = 0; i < 4; i++) + chip->op_rr[i][0] &= ~1; + + for (i = 0; i < 4; i++) + chip->op_sl[i][0] |= (chip->data >> (i + 4)) & 1; + for (i = 0; i < 4; i++) + chip->op_rr[i][0] |= (chip->data >> i) & 1; + } + if (sel_e0) + { + for (i = 0; i < 2; i++) + chip->op_wf[i][0] &= ~1; + + for (i = 0; i < 2; i++) + chip->op_wf[i][0] |= (chip->data >> i) & 1; + } + } + } + if (chip->clk2) + { + FMOPL2_DoShiftRegisters(chip, 1); + } + + //if (chip->clk2) // opt + { + int shift = 0; + + if (chip->fsm_out[13]) + shift = 8; + else if (chip->fsm_out[12]) + shift = 5; + else if (chip->fsm_out[15]) + shift = 2; + + chip->block = 0; + chip->fnum = 0; + for (i = 0; i < 3; i++) + chip->block |= ((chip->ch_block[i][1] >> shift) & 1) << i; + for (i = 0; i < 10; i++) + chip->fnum |= ((chip->ch_fnum[i][1] >> shift) & 1) << i; + chip->keyon = (chip->ch_keyon[1] >> shift) & 1; + chip->connect = (chip->ch_connect[1] >> shift) & 1; + + chip->fb = 0; + if (chip->fsm_out[13]) + shift = 5; + else if (chip->fsm_out[12]) + shift = 2; + else if (chip->fsm_out[15]) + shift = 8; + for (i = 0; i < 3; i++) + chip->fb |= ((chip->ch_fb[i][1] >> shift) & 1) << i; + + chip->multi = 0; + chip->tl = 0; + chip->ksl = 0; + chip->ar = 0; + chip->dr = 0; + chip->sl = 0; + chip->rr = 0; + chip->wf = 0; + + for (i = 0; i < 4; i++) + chip->multi |= ((chip->op_multi[i][1] >> 17) & 1) << i; + + chip->ksr = (chip->op_ksr[1] >> 17) & 1; + chip->egt = (chip->op_egt[1] >> 17) & 1; + chip->vib = (chip->op_vib[1] >> 17) & 1; + chip->am = (chip->op_am[1] >> 17) & 1; + + for (i = 0; i < 6; i++) + chip->tl |= ((chip->op_tl[i][1] >> 17) & 1) << i; + + for (i = 0; i < 2; i++) + chip->ksl |= ((chip->op_ksl[i][1] >> 17) & 1) << i; + + for (i = 0; i < 4; i++) + chip->ar |= ((chip->op_ar[i][1] >> 17) & 1) << i; + + for (i = 0; i < 4; i++) + chip->dr |= ((chip->op_dr[i][1] >> 17) & 1) << i; + + for (i = 0; i < 4; i++) + chip->sl |= ((chip->op_sl[i][1] >> 17) & 1) << i; + + for (i = 0; i < 4; i++) + chip->rr |= ((chip->op_rr[i][1] >> 17) & 1) << i; + + for (i = 0; i < 2; i++) + chip->wf |= ((chip->op_wf[i][1] >> 17) & 1) << i; + + } + + if (chip->clk1) + { + chip->connect_l[0] = (chip->connect_l[1] << 1) | chip->connect; + chip->fb_l[0][0] = chip->fb; + chip->fb_l[1][0] = chip->fb_l[0][1]; + } + if (chip->clk2) + { + chip->connect_l[1] = chip->connect_l[0]; + chip->fb_l[0][1] = chip->fb_l[0][0]; + chip->fb_l[1][1] = chip->fb_l[1][0]; + } + + if (chip->clk1) + { + chip->eg_load1_l = chip->fsm_out[8]; + chip->eg_load2_l = chip->fsm_out[9]; + chip->eg_load3_l = chip->eg_subcnt_l[1] && chip->eg_sync_l[1]; + } + chip->eg_load1 = !chip->eg_load1_l && chip->fsm_out[8]; + chip->eg_load2 = !chip->eg_load2_l && chip->fsm_out[9]; + chip->eg_load3 = !chip->eg_load3_l && chip->eg_subcnt_l[1] && chip->eg_sync_l[1]; + + { + + if (chip->eg_load1) + chip->trem_step = chip->am_step; + if (chip->eg_load2) + chip->trem_out = chip->trem_value[1] & 127; + + if (chip->clk1) + { + int bit = chip->trem_value[1] & 1; + int reset = chip->reset1 || (chip->reg_test & 128) != 0; + + int step = ((chip->trem_step || (chip->reg_test & 8) != 0) && (chip->fsm_out[9] || chip->trem_dir[1])) + && chip->fsm_out[14]; + int carry = chip->fsm_out[14] && chip->trem_carry[1]; + + bit += step + carry; + + int of = (chip->trem_out == 0) || (chip->trem_out & 105) == 105; + + chip->trem_carry[0] = (bit & 2) != 0; + chip->trem_value[0] = (chip->trem_value[1] >> 1) & 255; + if (!reset) + chip->trem_value[0] |= (bit & 1) << 8; + chip->trem_of[0] = of; + + if (reset) + chip->trem_dir[0] = 0; + else + chip->trem_dir[0] = chip->trem_dir[1] ^ (of && !chip->trem_of[1]); + } + if (chip->clk2) + { + chip->trem_carry[1] = chip->trem_carry[0]; + chip->trem_value[1] = chip->trem_value[0]; + chip->trem_of[1] = chip->trem_of[0]; + chip->trem_dir[1] = chip->trem_dir[0]; + } + } + + { + + if (chip->eg_load3) + { + chip->eg_timer_low = chip->eg_timer[1] & 3; + chip->eg_shift = 0; + if (chip->eg_timer_masked[1] & 0x1555) + chip->eg_shift |= 1; + if (chip->eg_timer_masked[1] & 0x666) + chip->eg_shift |= 2; + if (chip->eg_timer_masked[1] & 0x1878) + chip->eg_shift |= 4; + if (chip->eg_timer_masked[1] & 0x1f80) + chip->eg_shift |= 8; + } + + if (chip->clk1) + { + int bit = chip->eg_timer[1] & 1; + int bit2; + int carry = chip->eg_carry[1] || (chip->eg_subcnt[1] && chip->eg_sync_l[1]); + bit += carry; + + if (chip->reset1) + bit2 = 0; + else + bit2 = bit & 1; + + chip->eg_timer[0] = (chip->eg_timer[1] >> 1) & 0x1ffff; + chip->eg_timer[0] |= bit2 << 17; + chip->eg_carry[0] = (bit & 2) != 0; + chip->eg_sync_l[0] = chip->fsm_out[8]; + chip->eg_mask[0] = (chip->reset1 || chip->fsm_out[8]) ? 0 : + (chip->eg_mask[1] || bit2); + chip->eg_timer_masked[0] = (chip->eg_timer_masked[1] >> 1) & 0x1ffff; + if (!chip->eg_mask[1]) + chip->eg_timer_masked[0] |= bit2 << 17; + + if (chip->reset1) + chip->eg_subcnt[0] = 0; + else + chip->eg_subcnt[0] = chip->eg_subcnt[1] ^ chip->fsm_out[8]; + + chip->eg_subcnt_l[0] = chip->eg_subcnt[1]; + } + if (chip->clk2) + { + chip->eg_timer[1] = chip->eg_timer[0]; + chip->eg_carry[1] = chip->eg_carry[0]; + chip->eg_sync_l[1] = chip->eg_sync_l[0]; + chip->eg_mask[1] = chip->eg_mask[0]; + chip->eg_timer_masked[1] = chip->eg_timer_masked[0]; + chip->eg_subcnt[1] = chip->eg_subcnt[0]; + chip->eg_subcnt_l[1] = chip->eg_subcnt_l[0]; + } + } + + if (chip->clk1) + { + static const int eg_stephi[4][4] = { + { 0, 0, 0, 0 }, + { 1, 0, 0, 0 }, + { 1, 0, 1, 0 }, + { 1, 1, 1, 0 } + }; + + int state = 0; + if (chip->eg_state[0][1] & 0x20000) + state |= 1; + if (chip->eg_state[1][1] & 0x20000) + state |= 2; + + int dokon = state == eg_state_release && chip->keyon_comb; + int rate_sel = dokon ? eg_state_attack : state; + int rate = 0; + int ksr; + if (rate_sel == 0) + rate |= chip->ar; + if (rate_sel == 1) + rate |= chip->dr; + if (rate_sel == 3 || (rate_sel == 2 && !chip->egt)) + rate |= chip->rr; + + int sl = chip->sl; + if (chip->sl == 15) + sl |= 16; + + int ns = chip->reg_notesel ? (chip->fnum & 256) != 0 : (chip->fnum & 512) != 0; + + if (chip->ksr) + ksr = (chip->block << 1) | ns; + else + ksr = chip->block >> 1; + + int rate_hi = rate + (ksr >> 2); + if (rate_hi & 16) + rate_hi = 15; + + int maxrate = rate_hi == 15; + + int rate12 = rate_hi == 12; + int rate13 = rate_hi == 13; + int rate14 = rate_hi == 14; + + int inclow = 0; + + if (rate_hi < 12 && rate != 0 && chip->eg_subcnt[1]) + { + int sum = (rate_hi + chip->eg_shift) & 15; + switch (sum) + { + case 12: + inclow = 1; + break; + case 13: + inclow = (ksr & 2) != 0; + break; + case 14: + inclow = (ksr & 1) != 0; + break; + } + } + + int stephi = eg_stephi[ksr & 3][chip->eg_timer_low]; + + int step1 = 0; + int step2 = 0; + int step3 = 0; + + switch (rate_hi) + { + case 12: + step1 = stephi || chip->eg_subcnt[1]; + break; + case 13: + if (stephi) + step2 = 1; + else + step1 = 1; + break; + case 14: + if (stephi) + step3 = 1; + else + step2 = 1; + break; + case 15: + step3 = 1; + break; + } + + step1 |= inclow; + + int level = 0; + + for (i = 0; i < 9; i++) + { + level |= ((chip->eg_level[i][1] >> 17) & 1) << i; + } + + int slreach = (level >> 4) == sl; + int zeroreach = level == 0; + int silent = (level & 0x1f8) == 0x1f8; + + int nextstate = eg_state_attack; + + if (chip->reset1) + nextstate = eg_state_release; + else if (dokon) + nextstate = eg_state_attack; + else + { + if (!chip->keyon_comb) + nextstate = eg_state_release; + else if (state == eg_state_attack) + nextstate = zeroreach ? eg_state_decay : eg_state_attack; + else if (state == eg_state_decay) + nextstate = slreach ? eg_state_sustain : eg_state_decay; + else if (state == eg_state_sustain) + nextstate = eg_state_sustain; + else if (state == eg_state_release) + nextstate = eg_state_release; + } + + int linear = !dokon && !silent && ((state & 2) != 0 || (state == eg_state_decay && !slreach)); + int exponent = state == eg_state_attack && chip->keyon_comb && !maxrate && !zeroreach; + int instantattack = dokon && maxrate; + int mute = chip->reset1 || (state != eg_state_attack && silent && !dokon); + + int level2 = mute ? 0x1ff : (instantattack ? 0 : level); + + int add = 0; + int addshift = 0; + + if (exponent) + add |= (~level) >> 1; + if (linear) + add |= 4; + + if (step1) + addshift |= add >> 2; + if (step2) + addshift |= add >> 1; + if (step3) + addshift |= add >> 0; + + int levelnext = level2 + addshift; + + static const int eg_ksltable[16] = { + 0, 32, 40, 45, 48, 51, 53, 55, 56, 58, 59, 60, 61, 62, 63, 64 + }; + + int ksl; + ksl = eg_ksltable[chip->fnum >> 6] ^ 127; + + ksl += ((chip->block ^ 7) + 1) << 3; + if (ksl & 128) + ksl = 0; + else + ksl = (ksl ^ 63) & 63; + + static int eg_kslshift[4] = { + 31, 1, 2, 0 + }; + + ksl = (ksl << 2) >> eg_kslshift[chip->ksl]; + + int ksltl = ksl + (chip->tl << 2); + + int tremolo; + + if (!chip->am) + tremolo = 0; + else if (chip->reg_dv) + tremolo = chip->trem_out >> 2; + else + tremolo = chip->trem_out >> 4; + + int ksltltrem = ksltl + tremolo; + int levelof = 0; + + if (ksltltrem & 0x200) + levelof = 1; + + int totallevel = level + (ksltltrem & 0x1ff); + if (totallevel & 0x200) + levelof = 1; + + int totallevelclamp = (chip->reg_test & 1) != 0 ? 0 : (levelof ? 0x1ff : (totallevel & 0x1ff)); + + + chip->eg_dokon = dokon; + + chip->eg_state[0][0] = (chip->eg_state[0][1] << 1) | ((nextstate & 1) != 0); + chip->eg_state[1][0] = (chip->eg_state[1][1] << 1) | ((nextstate & 2) != 0); + + for (i = 0; i < 9; i++) + { + chip->eg_level[i][0] = (chip->eg_level[i][1] << 1) | ((levelnext >> i) & 1); + } + chip->eg_out[0] = totallevelclamp; + + if (chip->fsm_out[9]) + { + for (i = 0; i < 9; i++) + { + if (chip->eg_out[1] & (1 << i)) + chip->dbg_serial[0] |= 1 << (17 - i); + } + } + + chip->eg_mute[0] = (chip->eg_mute[1] << 1) | mute; + } + if (chip->clk2) + { + chip->eg_state[0][1] = chip->eg_state[0][0]; + chip->eg_state[1][1] = chip->eg_state[1][0]; + + for (i = 0; i < 9; i++) + { + chip->eg_level[i][1] = chip->eg_level[i][0]; + } + chip->eg_out[1] = chip->eg_out[0]; + chip->eg_mute[1] = chip->eg_mute[0]; + } + + if (chip->clk1) + { + static const int pg_multi[16] = { + 1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 20, 24, 24, 30, 30 + }; + int fnum = chip->fnum; + int freq; + int pg_add; + int vib_sel1 = (chip->vib_cnt[1] & 3) == 2; + int vib_sel2 = (chip->vib_cnt[1] & 1) == 1; + int vib_sh0 = chip->reg_dv && chip->vib && vib_sel1; + int vib_sh1 = (chip->reg_dv && chip->vib && vib_sel2) + || (!chip->reg_dv && chip->vib && vib_sel1); + int vib_sh2 = !chip->reg_dv && chip->vib && vib_sel2; + int vib_sign = (chip->vib_cnt[1] & 4) != 0 && chip->vib; + int vib_add = 0; + int pg_out = 0; + int phase; + int noise_bit; + if (vib_sh0) + vib_add |= (chip->fnum >> 7) & 7; + if (vib_sh1) + vib_add |= (chip->fnum >> 8) & 3; + if (vib_sh2) + vib_add |= (chip->fnum >> 9) & 1; + if (vib_sign) + { + vib_add ^= 1023; + } + fnum += vib_add; + fnum += vib_sign; + if (vib_sign) + fnum &= 1023; + + freq = (fnum << chip->block) >> 1; + + pg_add = (freq * pg_multi[chip->multi]) >> 1; + + for (i = 0; i < 19; i++) + { + pg_out |= ((chip->pg_phase[i][1] >> 17) & 1) << i; + } + + phase = ((chip->eg_dokon || (chip->reg_test & 4) != 0) ? 0 : pg_out) + pg_add; + + for (i = 0; i < 19; i++) + { + chip->pg_phase[i][0] = chip->pg_phase[i][1] << 1; + chip->pg_phase[i][0] |= (phase >> i) & 1; + } + + chip->dbg_serial[0] = chip->dbg_serial[1] >> 1; + + if (chip->fsm_out[9]) + { + chip->dbg_serial[0] |= pg_out & 511; + } + + noise_bit = ((chip->noise_lfsr[1] >> 22) ^ (chip->noise_lfsr[1] >> 8)) & 1; + + if ((chip->noise_lfsr[1] & 0x7fffff) == 0) + noise_bit |= 1; + + noise_bit |= (chip->reg_test & 128) != 0; + + chip->noise_lfsr[0] = (chip->noise_lfsr[1] << 1) | noise_bit; + } + if (chip->clk2) + { + for (i = 0; i < 19; i++) + { + chip->pg_phase[i][1] = chip->pg_phase[i][0]; + } + + chip->noise_lfsr[1] = chip->noise_lfsr[0]; + + chip->pg_out = 0; + for (i = 0; i < 10; i++) + { + chip->pg_out |= ((chip->pg_phase[i+9][1] >> 17) & 1) << i; + } + + chip->dbg_serial[1] = chip->dbg_serial[0]; + } + + { + int hh = chip->fsm_out[4] && chip->rhythm; + int sd = chip->fsm_out[7] && chip->rhythm; + int tc = chip->fsm_out[8] && chip->rhythm; + int rhy = (chip->fsm_out[4] || chip->fsm_out[7] || chip->fsm_out[8]) && chip->rhythm; + if (chip->clk1) + chip->hh_load = chip->fsm_out[4]; + if (!chip->hh_load && chip->fsm_out[5]) + { + chip->hh_bit2 = (chip->pg_out >> 2) & 1; + chip->hh_bit3 = (chip->pg_out >> 3) & 1; + chip->hh_bit7 = (chip->pg_out >> 7) & 1; + chip->hh_bit8 = (chip->pg_out >> 8) & 1; + } + if (chip->clk1) + chip->tc_load = tc; + if (!chip->tc_load && tc) + { + chip->tc_bit3 = (chip->pg_out >> 3) & 1; + chip->tc_bit5 = (chip->pg_out >> 5) & 1; + } + + if (chip->clk1) // opt + { + int rm_bit; + int noise = (chip->noise_lfsr[1] >> 22) & 1; + + rm_bit = (chip->hh_bit2 ^ chip->hh_bit7) + | (chip->tc_bit5 ^ chip->hh_bit3) + | (chip->tc_bit5 ^ chip->tc_bit3); + + chip->pg_out_rhy = 0; + if (!rhy) + chip->pg_out_rhy |= chip->pg_out; + if (hh) + { + chip->pg_out_rhy |= rm_bit << 9; + if (noise ^ rm_bit) + chip->pg_out_rhy |= 0xd0; + else + chip->pg_out_rhy |= 0x34; + } + if (sd) + chip->pg_out_rhy |= (chip->hh_bit8 << 9) | ((noise ^ chip->hh_bit8) << 8); + if (tc) + chip->pg_out_rhy |= (rm_bit << 9) | 0x100; + } + } + + { + + if (chip->clk1) + { + static const int logsin[128] = { + 0x6c3, 0x58b, 0x4e4, 0x471, 0x41a, 0x3d3, 0x398, 0x365, 0x339, 0x311, 0x2ed, 0x2cd, 0x2af, 0x293, 0x279, 0x261, + 0x24b, 0x236, 0x222, 0x20f, 0x1fd, 0x1ec, 0x1dc, 0x1cd, 0x1be, 0x1b0, 0x1a2, 0x195, 0x188, 0x17c, 0x171, 0x166, + 0x15b, 0x150, 0x146, 0x13c, 0x133, 0x129, 0x121, 0x118, 0x10f, 0x107, 0x0ff, 0x0f8, 0x0f0, 0x0e9, 0x0e2, 0x0db, + 0x0d4, 0x0cd, 0x0c7, 0x0c1, 0x0bb, 0x0b5, 0x0af, 0x0a9, 0x0a4, 0x09f, 0x099, 0x094, 0x08f, 0x08a, 0x086, 0x081, + 0x07d, 0x078, 0x074, 0x070, 0x06c, 0x068, 0x064, 0x060, 0x05c, 0x059, 0x055, 0x052, 0x04e, 0x04b, 0x048, 0x045, + 0x042, 0x03f, 0x03c, 0x039, 0x037, 0x034, 0x031, 0x02f, 0x02d, 0x02a, 0x028, 0x026, 0x024, 0x022, 0x020, 0x01e, + 0x01c, 0x01a, 0x018, 0x017, 0x015, 0x014, 0x012, 0x011, 0x00f, 0x00e, 0x00d, 0x00c, 0x00a, 0x009, 0x008, 0x007, + 0x007, 0x006, 0x005, 0x004, 0x004, 0x003, 0x002, 0x002, 0x001, 0x001, 0x001, 0x001, 0x000, 0x000, 0x000, 0x000 + }; + static const int logsin_d[128] = { + 0x196, 0x07c, 0x04a, 0x035, 0x029, 0x022, 0x01d, 0x019, 0x015, 0x013, 0x012, 0x00f, 0x00e, 0x00d, 0x00d, 0x00c, + 0x00b, 0x00a, 0x00a, 0x009, 0x009, 0x009, 0x008, 0x007, 0x007, 0x007, 0x007, 0x006, 0x007, 0x006, 0x006, 0x005, + 0x005, 0x005, 0x005, 0x005, 0x004, 0x005, 0x004, 0x004, 0x005, 0x004, 0x004, 0x003, 0x004, 0x003, 0x003, 0x003, + 0x003, 0x004, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x002, 0x003, 0x003, 0x003, 0x003, 0x002, 0x002, + 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x001, 0x002, 0x002, 0x002, 0x001, + 0x001, 0x001, 0x002, 0x002, 0x001, 0x001, 0x002, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, + 0x001, 0x001, 0x001, 0x000, 0x001, 0x000, 0x001, 0x000, 0x001, 0x001, 0x000, 0x000, 0x001, 0x001, 0x001, 0x001, + 0x000, 0x000, 0x000, 0x001, 0x000, 0x000, 0x001, 0x000, 0x001, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000 + }; + static const int pow[128] = { + 0x3f5, 0x3ea, 0x3df, 0x3d4, 0x3c9, 0x3bf, 0x3b4, 0x3a9, 0x39f, 0x394, 0x38a, 0x37f, 0x375, 0x36a, 0x360, 0x356, + 0x34c, 0x342, 0x338, 0x32e, 0x324, 0x31a, 0x310, 0x306, 0x2fd, 0x2f3, 0x2e9, 0x2e0, 0x2d6, 0x2cd, 0x2c4, 0x2ba, + 0x2b1, 0x2a8, 0x29e, 0x295, 0x28c, 0x283, 0x27a, 0x271, 0x268, 0x25f, 0x257, 0x24e, 0x245, 0x23c, 0x234, 0x22b, + 0x223, 0x21a, 0x212, 0x209, 0x201, 0x1f9, 0x1f0, 0x1e8, 0x1e0, 0x1d8, 0x1d0, 0x1c8, 0x1c0, 0x1b8, 0x1b0, 0x1a8, + 0x1a0, 0x199, 0x191, 0x189, 0x181, 0x17a, 0x172, 0x16b, 0x163, 0x15c, 0x154, 0x14d, 0x146, 0x13e, 0x137, 0x130, + 0x129, 0x122, 0x11b, 0x114, 0x10c, 0x106, 0x0ff, 0x0f8, 0x0f1, 0x0ea, 0x0e3, 0x0dc, 0x0d6, 0x0cf, 0x0c8, 0x0c2, + 0x0bb, 0x0b5, 0x0ae, 0x0a8, 0x0a1, 0x09b, 0x094, 0x08e, 0x088, 0x082, 0x07b, 0x075, 0x06f, 0x069, 0x063, 0x05d, + 0x057, 0x051, 0x04b, 0x045, 0x03f, 0x039, 0x033, 0x02d, 0x028, 0x022, 0x01c, 0x016, 0x011, 0x00b, 0x006, 0x000, + }; + static const int pow_d[128] = { + 0x005, 0x005, 0x005, 0x006, 0x006, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x006, 0x005, 0x005, + 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x004, 0x005, + 0x004, 0x004, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x004, 0x004, 0x004, 0x005, 0x004, 0x005, + 0x004, 0x004, 0x004, 0x005, 0x004, 0x004, 0x005, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, + 0x004, 0x003, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x003, 0x004, 0x004, 0x004, + 0x003, 0x003, 0x003, 0x003, 0x004, 0x003, 0x003, 0x003, 0x003, 0x003, 0x004, 0x004, 0x003, 0x003, 0x004, 0x003, + 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x004, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, + 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x002, 0x003, 0x003, 0x003, 0x003, 0x003, 0x002, 0x003, + }; + int phase = chip->pg_out_rhy + chip->op_mod[1]; + int sign = (phase & 512) != 0; + int quarter = (phase & 256) != 0; + phase &= 255; + if (quarter) + phase ^= 255; + + int ls = logsin[phase >> 1]; + if ((phase & 1) == 0) + ls += logsin_d[phase >> 1]; + + int att = chip->op_logsin[1] + (chip->eg_out[1] << 3); + if (att & 4096) + att = 4095; + + int pw = pow[(att >> 1) & 127]; + if ((att & 1) == 0) + pw += pow_d[(att >> 1) & 127]; + + int value = 0; + + if (chip->op_mute[1] & 2) + { + value = ((chip->op_pow[1] | 0x400) << 1) >> chip->op_shift[1]; + } + + if (chip->op_sign[1] & 2) + value ^= 8191; + + int sign_wf = sign && chip->wf == 0; + int mute_wf = !((chip->wf == 1 && sign) || (chip->wf == 3 && quarter)); + + int fb1 = 0; + int fb2 = 0; + for (i = 0; i < 14; i++) + { + int j = i; + if (i == 13) + j = 12; + fb1 |= ((chip->op_fb[0][j][1] >> 5) & 1) << i; + fb2 |= ((chip->op_fb[1][j][1] >> 5) & 1) << i; + } + int fb_sum = fb1 + fb2; + fb_sum &= 16383; + if (fb_sum & 8192) + fb_sum |= ~8191; + + int mod = 0; + + if (chip->fsm_out[2] && !(chip->connect_l[1] & 2)) + mod |= value & 1023; + if (chip->fsm_out[1]) + { + if (chip->fb_l[1][1]) + { + mod |= (fb_sum >> (9 - chip->fb_l[1][1])) & 1023; + } + } + + chip->op_logsin[0] = ls; + chip->op_shift[0] = (att >> 8) & 15; + chip->op_pow[0] = pw; + chip->op_mute[0] = (chip->op_mute[1] << 1) | mute_wf; + chip->op_sign[0] = (chip->op_sign[1] << 1) | sign_wf; + + for (i = 0; i < 13; i++) + { + int bit; + chip->op_fb[0][i][0] = chip->op_fb[0][i][1] << 1; + if (chip->fsm_out[2]) + bit = (value >> i) & 1; + else + bit = (chip->op_fb[0][i][1] >> 8) & 1; + chip->op_fb[0][i][0] |= bit; + chip->op_fb[1][i][0] = chip->op_fb[1][i][1] << 1; + if (chip->fsm_out[2]) + bit = (chip->op_fb[0][i][1] >> 8) & 1; + else + bit = (chip->op_fb[1][i][1] >> 8) & 1; + chip->op_fb[1][i][0] |= bit; + } + chip->op_mod[0] = mod & 1023; + + chip->op_value = value; + } + if (chip->clk2) + { + chip->op_logsin[1] = chip->op_logsin[0]; + chip->op_shift[1] = chip->op_shift[0]; + chip->op_pow[1] = chip->op_pow[0]; + chip->op_mute[1] = chip->op_mute[0]; + chip->op_sign[1] = chip->op_sign[0]; + + for (i = 0; i < 13; i++) + { + chip->op_fb[0][i][1] = chip->op_fb[0][i][0]; + chip->op_fb[1][i][1] = chip->op_fb[1][i][0]; + } + chip->op_mod[1] = chip->op_mod[0]; + } + } + + { + int accm_out = chip->fsm_out[8] ? (chip->accm_value[1] & 0x7fff) : 0; + if (chip->fsm_out[8] && !(chip->accm_value[1] & 0x20000)) + accm_out |= 0x8000; + + int top = (chip->accm_value[1] >> 15) & 7; + + int clamplow = top == 4 || top == 5 || top == 6; + int clamphigh = top == 3 || top == 2 || top == 1; + + if (chip->clk1) + chip->accm_load1_l = chip->fsm_out[8]; + chip->accm_load1 = !chip->accm_load1_l && chip->fsm_out[8]; + + if (chip->accm_load1) + { + chip->accm_clamplow = clamplow; + chip->accm_clamphigh = clamphigh; + chip->accm_top = (accm_out >> 9) & 127; + } + + if (chip->clk1) + { + int add = 0; + int op_out = chip->op_value; + if (op_out & 0x1000) + op_out |= ~0xfff; + if (!(chip->eg_mute[1] & 2) && chip->fsm_out[0]) + add = chip->fsm_out[11] ? (op_out * 2) : op_out; + + int value = chip->fsm_out[8] ? 0 : chip->accm_value[1]; + value += add; + + int sign = ((chip->accm_top & 64) != 0 && !chip->accm_clamplow) || chip->accm_clamphigh; + + int top_unsigned = chip->accm_top & 63; + if (!sign) + top_unsigned ^= 63; + + int shift = 0; + + if (top_unsigned & 32) + shift |= 7; + if ((top_unsigned & 48) == 16) + shift |= 6; + if ((top_unsigned & 56) == 8) + shift |= 5; + if ((top_unsigned & 60) == 4) + shift |= 4; + if ((top_unsigned & 62) == 2) + shift |= 3; + if (top_unsigned == 1) + shift |= 2; + if (top_unsigned == 0) + shift |= 1; + if (chip->accm_clamplow) + shift |= 7; + if (chip->accm_clamphigh) + shift |= 7; + + int accm_bit = 0; + + if (chip->fsm_out[6]) + accm_bit |= sign; + if (chip->accm_sel[1] & 1) + accm_bit |= (shift & 1) != 0; + if (chip->accm_sel[1] & 2) + accm_bit |= (shift & 2) != 0; + if (chip->accm_sel[1] & 4) + accm_bit |= (shift & 4) != 0; + + if ((chip->accm_sel[1] & 7) == 0 && !chip->fsm_out[6]) + { + if (top_unsigned & 32) + accm_bit |= (chip->accm_shifter[1] >> 6) & 1; + if ((top_unsigned & 48) == 16) + accm_bit |= (chip->accm_shifter[1] >> 5) & 1; + if ((top_unsigned & 56) == 8) + accm_bit |= (chip->accm_shifter[1] >> 4) & 1; + if ((top_unsigned & 60) == 4) + accm_bit |= (chip->accm_shifter[1] >> 3) & 1; + if ((top_unsigned & 62) == 2) + accm_bit |= (chip->accm_shifter[1] >> 2) & 1; + if (top_unsigned == 1) + accm_bit |= (chip->accm_shifter[1] >> 1) & 1; + if (top_unsigned == 0) + accm_bit |= chip->accm_shifter[1] & 1; + if (chip->accm_clamphigh) + accm_bit |= 1; + if (chip->accm_clamplow) + accm_bit = 0; + } + + chip->accm_value[0] = value & 0x3ffff; + chip->accm_shifter[0] = (chip->accm_shifter[1] >> 1) & 0x7fff; + if (chip->fsm_out[8]) + chip->accm_shifter[0] |= accm_out; + chip->accm_sel[0] = (chip->accm_sel[1] << 1) | chip->fsm_out[6]; + chip->accm_mo[0] = accm_bit; + } + if (chip->clk2) + { + chip->accm_value[1] = chip->accm_value[0]; + chip->accm_shifter[1] = chip->accm_shifter[0]; + chip->accm_sel[1] = chip->accm_sel[0]; + chip->accm_mo[1] = chip->accm_mo[0]; + } + } + +end: + chip->o_sh = chip->fsm_out[3]; + chip->o_mo = chip->accm_mo[1]; + chip->o_irq_pull = irq; + chip->o_sy = chip->clk1; + + if (chip->io_read0) + { + chip->io_data &= ~6; + if (chip->reg_test & 64) + chip->io_data |= chip->dbg_serial[1] & 1; + if (irq) + chip->io_data |= 128; + if (chip->t1_status) + chip->io_data |= 64; + if (chip->t2_status) + chip->io_data |= 32; + if (chip->unk_status1) + chip->io_data |= 16; + if (chip->unk_status2) + chip->io_data |= 8; + } + + if (chip->io_dir) + { + chip->data_o = chip->io_data; + chip->data_z = 0; + } + else + chip->data_z = 1; +} diff --git a/extern/YM3812-LLE/fmopl2.h b/extern/YM3812-LLE/fmopl2.h new file mode 100644 index 000000000..8363886f9 --- /dev/null +++ b/extern/YM3812-LLE/fmopl2.h @@ -0,0 +1,272 @@ +/* + * Copyright (C) 2023 nukeykt + * + * This file is part of YM3812-LLE. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * YM3812 emulator + * Thanks: + * Travis Goodspeed: + * YM3812 decap and die shot + * + */ + +#pragma once + +typedef struct +{ + int mclk; + int address; + int data_i; + int ic; + int cs; + int rd; + int wr; +} fmopl2_input_t; + +typedef struct +{ + fmopl2_input_t input; + + int mclk1; + int mclk2; + int clk1; + int clk2; + + int prescaler_reset_l[2]; + int prescaler_cnt[2]; + int prescaler_l1[2]; + int prescaler_l2[2]; + + int reset1; + + int fsm_reset_l[2]; + int fsm_reset; // wire + int fsm_cnt1[2]; + int fsm_cnt2[2]; + int fsm_cnt1_of; // wire + int fsm_cnt2_of; // wire + int fsm_sel[13]; + int fsm_cnt; // wire + int fsm_ch_out; + int fsm_do_fb; + int fsm_load_fb; + int fsm_l1[2]; + int fsm_l2[2]; + int fsm_l3[2]; + int fsm_l4[2]; + int fsm_l5[2]; + int fsm_l6[2]; + int fsm_out[16]; + + int io_rd; + int io_wr; + int io_cs; + int io_a0; + + int io_read0; + int io_read1; + int io_write; + int io_write0; + int io_write1; + int io_dir; + int io_data; + + int data_latch; + + int write0; + int write0_sr; + int write0_latch[6]; + int write1; + int write1_sr; + int write1_latch[6]; + + int reg_sel1; + int reg_sel2; + int reg_sel3; + int reg_sel4; + int reg_sel8; + int reg_selbd; + int reg_test; + int reg_timer1; + int reg_timer2; + int reg_notesel; + int reg_csm; + int reg_da; + int reg_dv; + int rhythm; + int reg_rh_kon; + int reg_sel4_wr; // wire + int reg_sel4_rst; // wire + int reg_t1_mask; + int reg_t2_mask; + int reg_t1_start; + int reg_t2_start; + int reg_mode_b3; + int reg_mode_b4; + + int t1_cnt[2]; + int t2_cnt[2]; + int t1_of[2]; + int t2_of[2]; + int t1_status; + int t2_status; + int unk_status1; + int unk_status2; + int timer_st_load_l; + int timer_st_load; + int t1_start; + int t1_start_l[2]; + int t2_start_l[2]; + int t1_load; // wire + int csm_load_l; + int csm_load; + int csm_kon; + int rh_sel0; + int rh_sel[2]; + + int keyon_comb; + int address; + int address_valid; + int address_valid_l[2]; + int address_valid2; + int data; + int slot_cnt1[2]; + int slot_cnt2[2]; + int slot_cnt; + int sel_ch; + + int ch_fnum[10][2]; + int ch_block[3][2]; + int ch_keyon[2]; + int ch_connect[2]; + int ch_fb[3][2]; + int op_multi[4][2]; + int op_ksr[2]; + int op_egt[2]; + int op_vib[2]; + int op_am[2]; + int op_tl[6][2]; + int op_ksl[2][2]; + int op_ar[4][2]; + int op_dr[4][2]; + int op_sl[4][2]; + int op_rr[4][2]; + int op_wf[2][2]; + int op_mod[2]; + int op_value; // wire + + int eg_load1_l; + int eg_load1; + int eg_load2_l; + int eg_load2; + int eg_load3_l; + int eg_load3; + + int trem_carry[2]; + int trem_value[2]; + int trem_dir[2]; + int trem_step; + int trem_out; + int trem_of[2]; + + int eg_timer[2]; + int eg_timer_masked[2]; + int eg_carry[2]; + int eg_mask[2]; + int eg_subcnt[2]; + int eg_subcnt_l[2]; + int eg_sync_l[2]; + int eg_timer_low; + int eg_shift; + int eg_state[2][2]; + int eg_level[9][2]; + int eg_out[2]; + int eg_dokon; // wire + int eg_mute[2]; + + int block; + int fnum; + int keyon; + int connect; + int connect_l[2]; + int fb; + int fb_l[2][2]; + int multi; + int ksr; + int egt; + int vib; + int am; + int tl; + int ksl; + int ar; + int dr; + int sl; + int rr; + int wf; + + int lfo_cnt[2]; + int t1_step; // wire + int t2_step; // wire + int am_step; // wire + int vib_step; // wire + int vib_cnt[2]; + int pg_phase[19][2]; + int dbg_serial[2]; + + int noise_lfsr[2]; + + int hh_load; + int tc_load; + int hh_bit2; + int hh_bit3; + int hh_bit7; + int hh_bit8; + int tc_bit3; + int tc_bit5; + int op_logsin[2]; + int op_shift[2]; + int op_pow[2]; + int op_mute[2]; + int op_sign[2]; + int op_fb[2][13][2]; + + int pg_out; // wire + int pg_out_rhy; // wire + + int accm_value[2]; + int accm_shifter[2]; + int accm_load1_l; + int accm_load1; + int accm_clamplow; + int accm_clamphigh; + int accm_top; + int accm_sel[2]; + int accm_mo[2]; + + int o_sh; + int o_mo; + int o_irq_pull; + int o_sy; + + int data_o; + int data_z; + + int o_clk1; + int o_clk2; + int o_reset1; + int o_write0; + int o_write1; + int o_data_latch; + +} fmopl2_t; + diff --git a/extern/YMF262-LLE/LICENSE b/extern/YMF262-LLE/LICENSE new file mode 100644 index 000000000..89e08fb00 --- /dev/null +++ b/extern/YMF262-LLE/LICENSE @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. And you must show them these terms so they know their +rights. + + We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. (Exception: if the Program itself is interactive but + does not normally print such an announcement, your work based on + the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Program, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. (This alternative is + allowed only for noncommercial distribution and only if you + received the program in object code or executable form with such + an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for +making modifications to it. For an executable work, complete source +code means all the source code for all modules it contains, plus any +associated interface definition files, plus the scripts used to +control compilation and installation of the executable. However, as a +special exception, the source code distributed need not include +anything that is normally distributed (in either source or binary +form) with the major components (compiler, kernel, and so on) of the +operating system on which the executable runs, unless that component +itself accompanies the executable. + +If distribution of executable or object code is made by offering +access to copy from a designated place, then offering equivalent +access to copy the source code from the same place counts as +distribution of the source code, even though third parties are not +compelled to copy the source along with the object code. + + 4. You may not copy, modify, sublicense, or distribute the Program +except as expressly provided under this License. Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + + 5. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + + 6. Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 7. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. For example, if a patent +license would not permit royalty-free redistribution of the Program by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under +any particular circumstance, the balance of the section is intended to +apply and the section as a whole is intended to apply in other +circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system, which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 8. If the distribution and/or use of the Program is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Program under this License +may add an explicit geographical distribution limitation excluding +those countries, so that distribution is permitted only in or among +countries not thus excluded. In such case, this License incorporates +the limitation as if written in the body of this License. + + 9. The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/extern/YMF262-LLE/Readme.md b/extern/YMF262-LLE/Readme.md new file mode 100644 index 000000000..f9cf1b581 --- /dev/null +++ b/extern/YMF262-LLE/Readme.md @@ -0,0 +1,13 @@ +# YMF262-LLE + +Yamaha YMF262 (OPL3) emulator using YMF262 die shot. + +Special thanks to John McMaster for decapping YMF262. + +https://siliconpr0n.org/map/yamaha/ymf262-m/ + +# MODIFICATION DISCLAIMER + +this is a modified version of YMF262-LLE which adds functions to allow its usage. + +the original Git commit is 63406354d05bc860a6762377ddbb9e2609bd6c36. diff --git a/extern/YMF262-LLE/fmopl3.c b/extern/YMF262-LLE/fmopl3.c new file mode 100644 index 000000000..4e82fb27c --- /dev/null +++ b/extern/YMF262-LLE/fmopl3.c @@ -0,0 +1,1646 @@ +/* + * Copyright (C) 2023 nukeykt + * + * This file is part of YMF262-LLE. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * YMF262 emulator + * Thanks: + * John McMaster (siliconpr0n.org): + * YMF262 decap and die shot + * + */ + +#include "fmopl3.h" + + +enum { + eg_state_attack = 0, + eg_state_decay, + eg_state_sustain, + eg_state_release +}; + +void FMOPL3_Clock(fmopl3_t *chip) +{ + int i; + + chip->mclk1 = !chip->input.mclk; + chip->mclk2 = chip->input.mclk; + + chip->io_rd = !chip->input.rd; + chip->io_wr = !chip->input.wr; + chip->io_cs = !chip->input.cs; + chip->io_a0 = chip->input.address & 1; + chip->io_a1 = (chip->input.address & 2) != 0; + + if (chip->mclk1) + { + chip->ic_latch[0] = (chip->ic_latch[1] << 1) | (!chip->input.ic); + } + if (chip->mclk2) + { + chip->ic_latch[1] = chip->ic_latch[0]; + + chip->reset0 = (chip->ic_latch[1] & 2) != 0; + } + + chip->io_read = !chip->reset0 && chip->io_cs && chip->io_rd && !chip->io_a0 && !chip->io_a1; + chip->io_write = !chip->reset0 && chip->io_cs && chip->io_wr; + chip->io_write0 = !chip->reset0 && chip->io_cs && chip->io_wr && !chip->io_a0; + chip->io_write1 = !chip->reset0 && chip->io_cs && chip->io_wr && chip->io_a0; + + if (chip->reset0) + chip->data_latch = 0; + else if (chip->io_write) + chip->data_latch = chip->input.data_i & 255; + if (chip->reset0) + chip->bank_latch = 0; + else if (chip->io_write0) + chip->bank_latch = chip->io_a1; + + if (chip->mclk2) + { + chip->prescaler1_reset[1] = chip->prescaler1_reset[0]; + chip->prescaler1_cnt[1] = chip->prescaler1_cnt[0]; + } + + int prescaler1_clk = (chip->reg_test1 & 0x40) != 0 ? chip->input.mclk : !(chip->prescaler1_cnt[1] & 2); + + chip->aclk1 = !prescaler1_clk; + chip->aclk2 = prescaler1_clk; + + if (chip->aclk2) + { + chip->prescaler2_reset_l[1] = chip->prescaler2_reset_l[0]; + chip->prescaler2_cnt[1] = chip->prescaler2_cnt[0]; + chip->prescaler2_l1[1] = chip->prescaler2_l1[0]; + chip->prescaler2_l3[1] = chip->prescaler2_l3[0]; + chip->prescaler2_l5[1] = chip->prescaler2_l5[0]; + chip->prescaler2_l6[1] = chip->prescaler2_l6[0]; + } + + + chip->clk1 = chip->prescaler2_l1[1] && !chip->prescaler2_l2; + chip->clk2 = chip->prescaler2_l3[1] && !chip->prescaler2_l4; + + chip->rclk1 = chip->prescaler2_l6[1]; + chip->rclk2 = chip->prescaler2_l5[1]; + + if (chip->aclk1) + { + + int ga = (chip->data_latch & 0xe0) != 0; + + int write0 = ga && chip->write0 && (chip->reg_test1 & 16) != 0; + int write = chip->write1 || write0; + + chip->ra_w1_l1 = write; + } + + if (chip->clk2) + { + chip->write0_l[1] = chip->write0_l[0]; + chip->write0_l[3] = chip->write0_l[2]; + + chip->write1_l[1] = chip->write1_l[0]; + chip->write1_l[3] = chip->write1_l[2]; + + chip->write0 = chip->write0_l[3] && !chip->write0_l[1]; + chip->write1 = chip->write1_l[3] && !chip->write1_l[1]; + } + + ////////////////////// + + //if (chip->o_clk1 == chip->clk1 && chip->o_clk2 == chip->clk2 && chip->o_rclk1 == chip->rclk1 && chip->o_rclk2 == chip->rclk2 && chip->o_reset0 == chip->reset0 + // && chip->o_ra_w1_l1 == chip->ra_w1_l1 && chip->o_bank_latch == chip->bank_latch && chip->o_data_latch == chip->data_latch) + // goto end; // opt + + chip->o_clk1 = chip->clk1; + chip->o_clk2 = chip->clk2; + chip->o_rclk1 = chip->rclk1; + chip->o_rclk2 = chip->rclk2; + chip->o_reset0 = chip->reset0; + chip->o_data_latch = chip->data_latch; + chip->o_bank_latch = chip->bank_latch; + chip->o_ra_w1_l1 = chip->ra_w1_l1; + + if (chip->reset0) + { + chip->reg_sel1 = 0; + chip->reg_sel2 = 0; + chip->reg_sel3 = 0; + chip->reg_sel4 = 0; + chip->reg_sel5 = 0; + chip->reg_sel8 = 0; + chip->reg_selbd = 0; + } + else if (chip->write0) + { + chip->reg_sel1 = chip->data_latch == 1; + chip->reg_sel2 = chip->data_latch == 2; + chip->reg_sel3 = chip->data_latch == 3; + chip->reg_sel4 = chip->data_latch == 4; + chip->reg_sel5 = chip->data_latch == 5; + chip->reg_sel8 = chip->data_latch == 8; + chip->reg_selbd = chip->data_latch == 0xbd; + } + + if (chip->reset0) + chip->reg_new = 0; + else if (chip->write1 && chip->bank_latch && chip->reg_sel5) + chip->reg_new = chip->data_latch & 1; + + int bank_masked = chip->reg_new && chip->bank_latch; + + if (chip->reset0) + { + chip->reg_test0 = 0; + chip->reg_test1 = 0; + chip->reg_timer1 = 0; + chip->reg_timer2 = 0; + chip->reg_notesel = 0; + chip->rhythm = 0; + chip->reg_rh_kon = 0; + chip->reg_da = 0; + chip->reg_dv = 0; + } + else if (chip->write1) + { + if (chip->reg_sel1 && !bank_masked) + chip->reg_test0 = chip->data_latch & 255; + if (chip->reg_sel2 && !bank_masked) + chip->reg_timer1 = chip->data_latch & 255; + if (chip->reg_sel3 && !bank_masked) + chip->reg_timer2 = chip->data_latch & 255; + if (chip->reg_sel8 && !bank_masked) + { + chip->reg_notesel = (chip->data_latch & 64) != 0; + } + if (chip->reg_selbd && !bank_masked) + { + chip->reg_rh_kon = chip->data_latch & 31; + chip->rhythm = (chip->data_latch & 32) != 0; + chip->reg_dv = (chip->data_latch & 64) != 0; + chip->reg_da = (chip->data_latch & 128) != 0; + } + if (chip->reg_sel1 && bank_masked) + chip->reg_test1 = chip->data_latch & 255; + if (chip->reg_sel4 && bank_masked) + chip->reg_4op = chip->data_latch & 63; + } + int reg_sel4_wr = chip->write1 && chip->reg_sel4 && !bank_masked && (chip->data_latch & 128) == 0; + int reg_sel4_rst = (chip->write1 && chip->reg_sel4 && !bank_masked && (chip->data_latch & 128) != 0) || chip->reset0; + + if (chip->reset0) + { + chip->reg_t1_mask = 0; + chip->reg_t2_mask = 0; + chip->reg_t1_start = 0; + chip->reg_t2_start = 0; + } + else if (reg_sel4_wr) + { + chip->reg_t1_mask = (chip->data_latch & 64) != 0; + chip->reg_t2_mask = (chip->data_latch & 32) != 0; + chip->reg_t1_start = (chip->data_latch & 1) != 0; + chip->reg_t2_start = (chip->data_latch & 2) != 0; + } + + chip->reset1 = chip->reset0 || (chip->reg_test1 & 0xc0) == 0xc0; + + { + //int bclk = !prescaler2_reset && chip->prescaler2_l7 && (chip->prescaler2_cnt[1] & 1) == 0; + + int ga = (chip->data_latch & 0xe0) != 0; + + if (chip->reset1) + chip->ra_address_latch = 0; + else if (chip->write0 && ga) + chip->ra_address_latch = (bank_masked << 8) | chip->data_latch; + if (chip->reset1) + chip->ra_address_good = 0; + else if (chip->write0) + chip->ra_address_good = ga; + if (chip->reset1) + chip->ra_data_latch = 0; + else if (chip->write1 && chip->ra_address_good) + chip->ra_data_latch = chip->data_latch; + + int write0 = ga && chip->write0 && (chip->reg_test1 & 16) != 0; + int write = chip->write1 || write0; + + if (chip->aclk1) + chip->ra_w1_l1 = write; + chip->ra_write = (write && !chip->ra_w1_l1) || (chip->reset1 && chip->clk2); + if (chip->clk1) + chip->ra_w1_l2 = write; + chip->ra_write_a = write && !chip->ra_w1_l2; + + if (chip->clk1) + { + chip->ra_rst_l[0] = chip->reset1; + int rst = (chip->reset1 && !chip->ra_rst_l[1]) || chip->fsm_out[5]; + + int of1 = (chip->ra_cnt1[1] & 5) == 5; + int of2 = (chip->ra_cnt2[1] & 2) == 2 && of1; + int of4 = (chip->ra_cnt4[1] & 2) == 2; + if (rst || of1) + chip->ra_cnt1[0] = 0; + else + chip->ra_cnt1[0] = (chip->ra_cnt1[1] + 1) & 7; + if (rst || of2) + chip->ra_cnt2[0] = 0; + else + chip->ra_cnt2[0] = (chip->ra_cnt2[1] + of1) & 3; + if (rst) + chip->ra_cnt3[0] = 0; + else + chip->ra_cnt3[0] = (chip->ra_cnt3[1] + of2) & 1; + + if (rst || of4 || of1) + chip->ra_cnt4[0] = 0; + else + chip->ra_cnt4[0] = (chip->ra_cnt4[1] + 1) & 3; + + } + if (chip->clk2) + { + chip->ra_rst_l[1] = chip->ra_rst_l[0]; + chip->ra_cnt1[1] = chip->ra_cnt1[0]; + chip->ra_cnt2[1] = chip->ra_cnt2[0]; + chip->ra_cnt3[1] = chip->ra_cnt3[0]; + chip->ra_cnt4[1] = chip->ra_cnt4[0]; + chip->ra_cnt = (chip->ra_cnt3[1] << 5) | (chip->ra_cnt2[1] << 3) | chip->ra_cnt1[1]; + } + + if (chip->ra_write || chip->clk1) + { + static const int ch_map[32] = { + 0, 1, 2, -1, + 3, 4, 5, -1, + 6, 7, 8, -1, + -1, -1, -1, -1, + 9, 10, 11, -1, + 12, 13, 14, -1, + 15, 16, 17, -1, + -1, -1, -1, -1 + }; + + static const int op_map[64] = { + 0, 1, 2, 3, 4, 5, -1, -1, + 6, 7, 8, 9, 10, 11, -1, -1, + 12, 13, 14, 15, 16, 17, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + 18, 19, 20, 21, 22, 23, -1, -1, + 24, 25, 26, 27, 28, 29, -1, -1, + 30, 31, 32, 33, 34, 35, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1 + }; + + int bank = (chip->ra_address_latch & 0x100) != 0; + int op_address = chip->ra_write_a ? ((chip->ra_address_latch & 0x1f) | (bank << 5)) : chip->ra_cnt; + int idx = op_map[op_address]; + if (chip->ra_write && idx != -1) + { + if ((chip->ra_address_latch & 0xe0) == 0x20 || write0 || chip->reset1) + { + chip->ra_multi[idx] = chip->ra_data_latch & 15; + chip->ra_ksr[idx] = (chip->ra_data_latch >> 4) & 1; + chip->ra_egt[idx] = (chip->ra_data_latch >> 5) & 1; + chip->ra_vib[idx] = (chip->ra_data_latch >> 6) & 1; + chip->ra_am[idx] = (chip->ra_data_latch >> 7) & 1; + } + if ((chip->ra_address_latch & 0xe0) == 0x40 || write0 || chip->reset1) + { + chip->ra_tl[idx] = chip->ra_data_latch & 63; + chip->ra_ksl[idx] = (chip->ra_data_latch >> 6) & 3; + } + if ((chip->ra_address_latch & 0xe0) == 0x60 || write0 || chip->reset1) + { + chip->ra_dr[idx] = chip->ra_data_latch & 15; + chip->ra_ar[idx] = (chip->ra_data_latch >> 4) & 15; + } + if ((chip->ra_address_latch & 0xe0) == 0x80 || write0 || chip->reset1) + { + chip->ra_rr[idx] = chip->ra_data_latch & 15; + chip->ra_sl[idx] = (chip->ra_data_latch >> 4) & 15; + } + if ((chip->ra_address_latch & 0xe0) == 0xe0 || write0 || chip->reset1) + { + int data = chip->ra_data_latch & 3; + if (chip->reg_new) + data |= chip->ra_data_latch & 4; + chip->ra_wf[idx] = data; + } + } + int ch_address_write = chip->ra_address_latch & 15; + int add = 0; + if (ch_address_write == 3 || ch_address_write == 4 || ch_address_write == 5) + add |= 1; + if (ch_address_write == 6 || ch_address_write == 7 || ch_address_write == 8) + add |= 2; + int ch_address_mapped = (ch_address_write & 1) + (add & 1); + ch_address_mapped |= add & 2; + ch_address_mapped += ch_address_write & 14; + ch_address_mapped &= 15; + ch_address_mapped |= bank << 4; + int ch_address_mapped2 = ch_address_mapped & 3; + if ((ch_address_mapped & 12) == 8) + ch_address_mapped2 |= 4; + if ((ch_address_mapped & 12) == 0) + ch_address_mapped2 |= 8; + if ((ch_address_mapped & 28) == 0 || (ch_address_mapped & 28) == 20 || (ch_address_mapped & 28) == 24) + ch_address_mapped2 |= 16; + + + int ch_address_read = (chip->ra_cnt4[1] & 3) | (chip->ra_cnt2[1] << 2) | (chip->ra_cnt3[1] << 4); + int ch_address = chip->ra_write_a ? ch_address_mapped : ch_address_read; + int ch_address_read_4op = ch_address_read; + if ((chip->ra_cnt2[1] & 2) == 0) + { + switch (chip->ra_cnt3[1] * 4 + chip->ra_cnt4[1]) + { + case 0: // 0, 3, 6, 9 + if (chip->reg_4op & 1) + ch_address_read_4op &= ~4; + break; + case 1: // 1, 4, 7, 10 + if (chip->reg_4op & 2) + ch_address_read_4op &= ~4; + break; + case 2: // 2, 5, 8, 11 + if (chip->reg_4op & 4) + ch_address_read_4op &= ~4; + break; + case 4: // 0, 3, 6, 9 + if (chip->reg_4op & 8) + ch_address_read_4op &= ~4; + break; + case 5: // 1, 4, 7, 10 + if (chip->reg_4op & 16) + ch_address_read_4op &= ~4; + break; + case 6: // 2, 5, 8, 11 + if (chip->reg_4op & 32) + ch_address_read_4op &= ~4; + break; + } + } + int ch_address_4op = chip->ra_write_a ? ch_address_mapped : ch_address_read_4op; + int ch_address_fb = chip->ra_write_a ? ch_address_mapped2 : ch_address_read; + + int idx1 = ch_map[ch_address]; + int idx2 = ch_map[ch_address_4op]; + int idx3 = ch_map[ch_address_fb]; + if (chip->ra_write && idx1 != -1) + { + if ((chip->ra_address_latch & 0xf0) == 0xc0 || write0 || chip->reset1) + { + chip->ra_connect[idx1] = chip->ra_data_latch & 1; + int pan_data = 0; + if (!chip->reg_new || chip->reset1) + pan_data |= 3; + if (chip->reg_new) + pan_data |= (chip->ra_data_latch >> 4) & 15; + chip->ra_pan[idx1] = pan_data; + } + } + if (chip->ra_write && idx2 != -1) + { + if ((chip->ra_address_latch & 0xf0) == 0xa0 || write0 || chip->reset1) + { + chip->ra_fnum[idx2] &= 0x300; + chip->ra_fnum[idx2] |= chip->ra_data_latch & 0xff; + } + if ((chip->ra_address_latch & 0xf0) == 0xb0 || write0 || chip->reset1) + { + chip->ra_fnum[idx2] &= 0xff; + chip->ra_fnum[idx2] |= (chip->ra_data_latch & 3) << 8; + chip->ra_block[idx2] = (chip->ra_data_latch >> 2) & 7; + chip->ra_keyon[idx2] = (chip->ra_data_latch >> 5) & 1; + } + } + if (chip->ra_write && idx3 != -1) + { + if ((chip->ra_address_latch & 0xf0) == 0xc0 || write0 || chip->reset1) + { + chip->ra_connect_pair[idx3] = chip->ra_data_latch & 1; + chip->ra_fb[idx3] = (chip->ra_data_latch >> 1) & 7; + } + } + + if (chip->clk1) + { + if (idx != -1) + { + chip->multi[0] = chip->ra_multi[idx]; + chip->ksr[0] = chip->ra_ksr[idx]; + chip->egt[0] = chip->ra_egt[idx]; + chip->am[0] = chip->ra_am[idx]; + chip->vib[0] = chip->ra_vib[idx]; + chip->tl[0] = chip->ra_tl[idx]; + chip->ksl[0] = chip->ra_ksl[idx]; + chip->ar[0] = chip->ra_ar[idx]; + chip->dr[0] = chip->ra_dr[idx]; + chip->sl[0] = chip->ra_sl[idx]; + chip->rr[0] = chip->ra_rr[idx]; + chip->wf[0] = chip->ra_wf[idx]; + } + if (idx1 != -1) + { + chip->connect[0] = chip->ra_connect[idx1]; + chip->pan[0] = chip->ra_pan[idx1]; + } + if (idx2 != -1) + { + chip->fnum[0] = chip->ra_fnum[idx2]; + chip->block[0] = chip->ra_block[idx2]; + chip->keyon[0] = chip->ra_keyon[idx2]; + } + if (idx3 != -1) + { + chip->connect_pair[0] = chip->ra_connect_pair[idx3]; + chip->fb[0] = chip->ra_fb[idx3]; + } + } + } + if (chip->clk2) + { + chip->multi[1] = chip->multi[0]; + chip->ksr[1] = chip->ksr[0]; + chip->egt[1] = chip->egt[0]; + chip->am[1] = chip->am[0]; + chip->vib[1] = chip->vib[0]; + chip->tl[1] = chip->tl[0]; + chip->ksl[1] = chip->ksl[0]; + chip->ar[1] = chip->ar[0]; + chip->dr[1] = chip->dr[0]; + chip->sl[1] = chip->sl[0]; + chip->rr[1] = chip->rr[0]; + chip->wf[1] = chip->wf[0]; + + chip->connect[1] = chip->connect[0]; + chip->pan[1] = chip->pan[0]; + + chip->fnum[1] = chip->fnum[0]; + chip->block[1] = chip->block[0]; + chip->keyon[1] = chip->keyon[0]; + + chip->connect_pair[1] = chip->connect_pair[0]; + chip->fb[1] = chip->fb[0]; + } + } + + if (chip->clk1) + { + chip->connect_l[0] = (chip->connect_l[1] << 1) | chip->connect[1]; + chip->connect_pair_l[0] = (chip->connect_pair_l[1] << 1) | chip->connect_pair[1]; + chip->fb_l[0][0] = chip->fb[1]; + chip->fb_l[1][0] = chip->fb_l[0][1]; + chip->pan_l[0][0] = chip->pan[1]; + chip->pan_l[1][0] = chip->pan_l[0][1]; + } + if (chip->clk2) + { + chip->connect_l[1] = chip->connect_l[0]; + chip->connect_pair_l[1] = chip->connect_pair_l[0]; + chip->fb_l[0][1] = chip->fb_l[0][0]; + chip->fb_l[1][1] = chip->fb_l[1][0]; + chip->pan_l[0][1] = chip->pan_l[0][0]; + chip->pan_l[1][1] = chip->pan_l[1][0]; + } + + { + int fsm_4op = 0; + switch (chip->fsm_cnt) + { + case 5: // 5 + fsm_4op = (chip->reg_4op & 1) != 0; + break; + case 8: // 6 + fsm_4op = (chip->reg_4op & 2) != 0; + break; + case 9: // 7 + fsm_4op = (chip->reg_4op & 4) != 0; + break; + case 37: // 23 + fsm_4op = (chip->reg_4op & 8) != 0; + break; + case 40: // 24 + fsm_4op = (chip->reg_4op & 16) != 0; + break; + case 41: // 25 + fsm_4op = (chip->reg_4op & 32) != 0; + break; + } + int con_4op = fsm_4op && (chip->fsm_l10[1] & 4) != 0; // 01 connect + + if (chip->clk1) + { + int fsm_reset = (chip->fsm_reset_l[1] & 2) == 0 && chip->reset1; + chip->fsm_reset_l[0] = (chip->fsm_reset_l[1] << 1) | chip->reset1; + + int fsm_of1 = (chip->fsm_cnt1[1] & 5) == 5; + int fsm_of2 = (chip->fsm_cnt2[1] & 2) == 2 && fsm_of1; + + if (fsm_reset || fsm_of1) + chip->fsm_cnt1[0] = 0; + else + chip->fsm_cnt1[0] = (chip->fsm_cnt1[1] + 1) & 7; + + if (fsm_reset || fsm_of2) + chip->fsm_cnt2[0] = 0; + else + chip->fsm_cnt2[0] = (chip->fsm_cnt2[1] + fsm_of1) & 3; + + if (fsm_reset) + chip->fsm_cnt3[0] = 0; + else + chip->fsm_cnt3[0] = (chip->fsm_cnt3[1] + fsm_of2) & 1; + + chip->fsm_l1[0] = chip->fsm_cnt == 53; + chip->fsm_l2[0] = chip->fsm_cnt == 16; + chip->fsm_l3[0] = chip->fsm_cnt == 20; + chip->fsm_l4[0] = chip->fsm_cnt == 52; + chip->fsm_l5[0] = (chip->fsm_l5[1] << 1) | ((chip->fsm_cnt & 56) == 0); + chip->fsm_l6[0] = (chip->fsm_l6[1] << 1) | ((chip->fsm_cnt & 56) == 8 || (chip->fsm_cnt & 62) == 16); + chip->fsm_l7[0] = (chip->fsm_l7[1] << 1) | ((chip->fsm_cnt & 56) == 40 || (chip->fsm_cnt & 62) == 48); + chip->fsm_l8[0] = (chip->fsm_l8[1] << 1) | ((chip->fsm_cnt & 48) == 16); + chip->fsm_l9[0] = (chip->fsm_l9[1] << 1) | con_4op; + chip->fsm_l10[0] = (chip->fsm_l10[1] << 1) | ((chip->connect_l[1] & 2) == 0 && (chip->connect_pair_l[1] & 2) != 0); + } + if (chip->clk2) + { + chip->fsm_reset_l[1] = chip->fsm_reset_l[0]; + chip->fsm_cnt1[1] = chip->fsm_cnt1[0]; + chip->fsm_cnt2[1] = chip->fsm_cnt2[0]; + chip->fsm_cnt3[1] = chip->fsm_cnt3[0]; + + chip->fsm_cnt = (chip->fsm_cnt3[1] << 5) | (chip->fsm_cnt2[1] << 3) | chip->fsm_cnt1[1]; + + chip->fsm_l1[1] = chip->fsm_l1[0]; + chip->fsm_l2[1] = chip->fsm_l2[0]; + chip->fsm_l3[1] = chip->fsm_l3[0]; + chip->fsm_l4[1] = chip->fsm_l4[0]; + chip->fsm_l5[1] = chip->fsm_l5[0]; + chip->fsm_l6[1] = chip->fsm_l6[0]; + chip->fsm_l7[1] = chip->fsm_l7[0]; + chip->fsm_l8[1] = chip->fsm_l8[0]; + chip->fsm_l9[1] = chip->fsm_l9[0]; + chip->fsm_l10[1] = chip->fsm_l10[0]; + } + { + chip->fsm_out[0] = chip->fsm_l1[1]; // 0 + chip->fsm_out[1] = chip->fsm_cnt == 16; // 12 + chip->fsm_out[2] = chip->fsm_l2[1]; // 13 + chip->fsm_out[3] = chip->fsm_cnt == 20; // 16 + chip->fsm_out[4] = chip->fsm_l3[1]; // 17 + chip->fsm_out[5] = chip->fsm_cnt == 52; // 34 + chip->fsm_out[6] = chip->fsm_l4[1]; // 35 + chip->fsm_out[7] = (chip->fsm_l5[1] & 4) != 0 || ((chip->fsm_cnt & 56) == 0); // 0-8 + chip->fsm_out[8] = (chip->fsm_cnt & 32) == 0; + chip->fsm_out[9] = (chip->fsm_l6[1] & 2) != 0; + chip->fsm_out[10] = (chip->fsm_l7[1] & 2) != 0; + chip->fsm_out[11] = chip->rhythm && (chip->fsm_l8[1] & 2) != 0; // r 14, 15, 16, 17, 18, 19 + + int fsm_mc = !((chip->fsm_cnt & 5) == 4 || (chip->fsm_cnt & 2) != 0); + int fsm_mc_4op = fsm_mc && !fsm_4op; + int rhy_19_20 = chip->rhythm && (chip->fsm_cnt == 19 || chip->fsm_cnt == 20); + + chip->fsm_out[12] = fsm_mc_4op && !(chip->rhythm && (chip->fsm_cnt == 16 || chip->fsm_cnt == 17)); // feedback + chip->fsm_out[14] = con_4op || (!fsm_4op && !(chip->fsm_l9[1] & 4) && (chip->connect_l[1] & 2) != 0); // connect + chip->fsm_out[13] = !(chip->rhythm && chip->fsm_cnt == 18) && (fsm_mc_4op || rhy_19_20 || chip->fsm_out[14]); // output + chip->fsm_out[15] = !fsm_mc && !rhy_19_20; // load fb + chip->fsm_out[16] = !fsm_mc_4op && !rhy_19_20; // modulate + } + } + + if (chip->clk1) + chip->timer_st_load_l = chip->fsm_out[6]; + chip->timer_st_load = chip->fsm_out[6] && !chip->timer_st_load_l; + + if (chip->timer_st_load) + { + chip->t1_start = chip->reg_t1_start; + chip->t2_start = chip->reg_t2_start; + } + + if (chip->clk1) + { + int lfo = chip->lfo_cnt[1]; + int add = chip->fsm_out[6]; + int reset = (chip->reg_test0 & 2) != 0 || chip->reset1; + + chip->lfo_cnt[0] = reset ? 0 : (lfo + add) & 1023; + chip->vib_cnt[0] = reset ? 0 : (chip->vib_cnt[1] + chip->vib_step) & 7; + } + if (chip->clk2) + { + chip->lfo_cnt[1] = chip->lfo_cnt[0]; + chip->vib_cnt[1] = chip->vib_cnt[0]; + } + + { + int lfo = chip->lfo_cnt[1]; + int add = chip->fsm_out[6]; + + chip->t1_step = (((lfo & 3) + add) & 4) != 0; + chip->t2_step = (((lfo & 15) + add) & 16) != 0; + chip->am_step = (((lfo & 63) + add) & 64) != 0; + chip->vib_step = (((lfo & 1023) + add) & 1024) != 0; + chip->vib_step |= (chip->reg_test0 & 16) != 0 && add; + } + + if (chip->clk1) + { + int value = (chip->t1_of[1] || (chip->t1_start_l[1] & 3) == 1) ? chip->reg_timer1 : chip->t1_cnt[1]; + value += ((chip->t1_start_l[1] & 1) != 0 && chip->t1_step) || (chip->reg_test1 & 8) != 0; + chip->t1_of[0] = (value & 256) != 0; + chip->t1_cnt[0] = (chip->t1_start_l[1] & 1) == 0 ? 0 : (value & 255); + + value = (chip->t2_of[1] || (chip->t2_start_l[1] & 3) == 1) ? chip->reg_timer2 : chip->t2_cnt[1]; + value += ((chip->t2_start_l[1] & 1) != 0 && chip->t2_step) || (chip->reg_test1 & 8) != 0; + chip->t2_of[0] = (value & 256) != 0; + chip->t2_cnt[0] = (chip->t2_start_l[1] & 1) == 0 ? 0 : (value & 255); + + chip->t1_start_l[0] = (chip->t1_start_l[1] << 1) | chip->t1_start; + chip->t2_start_l[0] = (chip->t2_start_l[1] << 1) | chip->t2_start; + } + if (chip->clk2) + { + chip->t1_cnt[1] = chip->t1_cnt[0]; + chip->t1_of[1] = chip->t1_of[0]; + chip->t2_cnt[1] = chip->t2_cnt[0]; + chip->t2_of[1] = chip->t2_of[0]; + + chip->t1_start_l[1] = chip->t1_start_l[0]; + chip->t2_start_l[1] = chip->t2_start_l[0]; + } + + if (reg_sel4_rst || chip->reg_t1_mask) + chip->t1_status = 0; + else if (chip->t1_of[1]) + chip->t1_status = 1; + + if (reg_sel4_rst || chip->reg_t2_mask) + chip->t2_status = 0; + else if (chip->t2_of[1]) + chip->t2_status = 1; + + chip->rh_sel0 = chip->rhythm && chip->fsm_out[1]; + + if (chip->clk1) + { + chip->rh_sel[0] = (chip->rh_sel[1] << 1) | chip->rh_sel0; + } + if (chip->clk2) + { + chip->rh_sel[1] = chip->rh_sel[0]; + } + + chip->keyon_comb = chip->keyon[1] + || (chip->rh_sel0 && (chip->reg_rh_kon & 16) != 0) // bd0 + || ((chip->rh_sel[1] & 1) != 0 && (chip->reg_rh_kon & 1) != 0) // hh + || ((chip->rh_sel[1] & 2) != 0 && (chip->reg_rh_kon & 4) != 0) // tom + || ((chip->rh_sel[1] & 4) != 0 && (chip->reg_rh_kon & 16) != 0) // bd1 + || ((chip->rh_sel[1] & 8) != 0 && (chip->reg_rh_kon & 8) != 0) // sd + || ((chip->rh_sel[1] & 16) != 0 && (chip->reg_rh_kon & 2) != 0); // tc + + + if (chip->clk1) + { + chip->trem_load_l = chip->fsm_out[0]; + chip->trem_st_load_l = chip->fsm_out[6]; + chip->eg_load_l = chip->eg_load_l1[1]; + } + chip->trem_load = !chip->trem_load_l && chip->fsm_out[0]; + chip->trem_st_load = !chip->trem_st_load_l && chip->fsm_out[6]; + chip->eg_load = !chip->eg_load_l && chip->eg_load_l1[1]; + + { + if (chip->trem_st_load) + chip->trem_step = chip->am_step; + if (chip->trem_load) + chip->trem_out = chip->trem_value[1] & 127; + + if (chip->clk1) + { + int bit = chip->trem_value[1] & 1; + int reset = chip->reset1 || (chip->reg_test0 & 2) != 0; + + int step = ((chip->trem_step || (chip->reg_test0 & 16) != 0) && (chip->fsm_out[0] || chip->trem_dir[1])) + && chip->fsm_out[7]; + int carry = chip->fsm_out[7] && chip->trem_carry[1]; + + bit += step + carry; + + int of = (chip->trem_out == 0) || (chip->trem_out & 105) == 105; + + chip->trem_carry[0] = (bit & 2) != 0; + chip->trem_value[0] = (chip->trem_value[1] >> 1) & 255; + if (!reset) + chip->trem_value[0] |= (bit & 1) << 8; + chip->trem_of[0] = of; + + if (reset) + chip->trem_dir[0] = 0; + else + chip->trem_dir[0] = chip->trem_dir[1] ^ (of && !chip->trem_of[1]); + } + if (chip->clk2) + { + chip->trem_carry[1] = chip->trem_carry[0]; + chip->trem_value[1] = chip->trem_value[0]; + chip->trem_of[1] = chip->trem_of[0]; + chip->trem_dir[1] = chip->trem_dir[0]; + } + } + + { + + if (chip->reset1) + { + chip->eg_timer_low = 0; + chip->eg_shift = 0; + } + else if (chip->eg_load) + { + chip->eg_timer_low = chip->eg_timer_o[3] | (chip->eg_timer_o[1] << 1); + chip->eg_shift = 0; + if (chip->eg_timer_masked[1] & 0x1555) + chip->eg_shift |= 1; + if (chip->eg_timer_masked[1] & 0x666) + chip->eg_shift |= 2; + if (chip->eg_timer_masked[1] & 0x1878) + chip->eg_shift |= 4; + if (chip->eg_timer_masked[1] & 0x1f80) + chip->eg_shift |= 8; + } + + if (chip->clk1) + { + int bit = chip->eg_timer_o[3]; + int bit2; + int carry = chip->eg_carry[1] || (chip->eg_subcnt[1] && chip->eg_sync_l[1]); + bit += carry; + + int rst = chip->reset1 || (chip->reg_test1 & 8) != 0; + + if (rst) + bit2 = 0; + else + bit2 = bit & 1; + + chip->eg_timer_i = bit2; + chip->eg_carry[0] = (bit & 2) != 0; + chip->eg_sync_l[0] = chip->fsm_out[6]; + chip->eg_mask[0] = (rst || chip->fsm_out[6]) ? 0 : + (chip->eg_mask[1] || bit2); + chip->eg_timer_masked[0] = (chip->eg_timer_masked[1] >> 1) & 0x7ffffffffLL; + if (!chip->eg_mask[1]) + chip->eg_timer_masked[0] |= ((int64_t)bit2) << 35; + if (!chip->eg_timer_dbg[1] && (chip->reg_test0 & 64) != 0) + chip->eg_timer_masked[0] |= 1LL << 35; + + if (chip->reset1) + chip->eg_subcnt[0] = 0; + else + chip->eg_subcnt[0] = chip->eg_subcnt[1] ^ chip->fsm_out[6]; + + chip->eg_load_l1[0] = chip->eg_subcnt[1] && chip->fsm_out[6]; + + chip->eg_timer_dbg[0] = (chip->reg_test0 & 64) != 0; + } + if (chip->clk2) + { + chip->eg_carry[1] = chip->eg_carry[0]; + chip->eg_sync_l[1] = chip->eg_sync_l[0]; + chip->eg_mask[1] = chip->eg_mask[0]; + chip->eg_timer_masked[1] = chip->eg_timer_masked[0]; + chip->eg_subcnt[1] = chip->eg_subcnt[0]; + chip->eg_load_l1[1] = chip->eg_load_l1[0]; + chip->eg_timer_dbg[1] = chip->eg_timer_dbg[0]; + } + } + + if (chip->clk1) + { + static const int eg_stephi[4][4] = { + { 0, 0, 0, 0 }, + { 1, 0, 0, 0 }, + { 1, 0, 1, 0 }, + { 1, 1, 1, 0 } + }; + + int rst = chip->reset1 || (chip->reg_test1 & 32) != 0; + + int state = chip->eg_state_o[3]; + int dokon = state == eg_state_release && chip->keyon_comb; + int rate_sel = dokon ? eg_state_attack : state; + int rate = 0; + int ksr; + if (rate_sel == 0) + rate |= chip->ar[1]; + if (rate_sel == 1) + rate |= chip->dr[1]; + if (rate_sel == 3 || (rate_sel == 2 && !chip->egt[1])) + rate |= chip->rr[1]; + + int sl = chip->sl[1]; + if (chip->sl[1] == 15) + sl |= 16; + + int ns = chip->reg_notesel ? (chip->fnum[1] & 256) != 0 : (chip->fnum[1] & 512) != 0; + + if (chip->ksr[1]) + ksr = (chip->block[1] << 1) | ns; + else + ksr = chip->block[1] >> 1; + + int rate_hi = rate + (ksr >> 2); + if (rate_hi & 16) + rate_hi = 15; + + int maxrate = rate_hi == 15; + + int rate12 = rate_hi == 12; + int rate13 = rate_hi == 13; + int rate14 = rate_hi == 14; + + int inclow = 0; + + if (rate_hi < 12 && rate != 0 && chip->eg_subcnt[1]) + { + int sum = (rate_hi + chip->eg_shift) & 15; + switch (sum) + { + case 12: + inclow = 1; + break; + case 13: + inclow = (ksr & 2) != 0; + break; + case 14: + inclow = (ksr & 1) != 0; + break; + } + } + + int stephi = eg_stephi[ksr & 3][chip->eg_timer_low]; + + int step1 = 0; + int step2 = 0; + int step3 = 0; + + switch (rate_hi) + { + case 12: + step1 = stephi || chip->eg_subcnt[1]; + break; + case 13: + if (stephi) + step2 = 1; + else + step1 = 1; + break; + case 14: + if (stephi) + step3 = 1; + else + step2 = 1; + break; + case 15: + step3 = 1; + break; + } + + step1 |= inclow; + + int level = chip->eg_level_o[3]; + int slreach = (level >> 4) == sl; + int zeroreach = level == 0; + int silent = (level & 0x1f8) == 0x1f8; + + static const int eg_ksltable[16] = { + 0, 32, 40, 45, 48, 51, 53, 55, 56, 58, 59, 60, 61, 62, 63, 64 + }; + + int nextstate = eg_state_attack; + + if (rst) + nextstate = eg_state_release; + else if (dokon) + nextstate = eg_state_attack; + else + { + if (!chip->keyon_comb) + nextstate = eg_state_release; + else if (state == eg_state_attack) + nextstate = zeroreach ? eg_state_decay : eg_state_attack; + else if (state == eg_state_decay) + nextstate = slreach ? eg_state_sustain : eg_state_decay; + else if (state == eg_state_sustain) + nextstate = eg_state_sustain; + else if (state == eg_state_release) + nextstate = eg_state_release; + } + + int linear = !dokon && !silent && ((state & 2) != 0 || (state == eg_state_decay && !slreach)); + int exponent = state == eg_state_attack && chip->keyon_comb && !maxrate && !zeroreach; + int instantattack = (dokon && maxrate) || (chip->reg_test0 & 16) != 0; + int mute = rst || (state != eg_state_attack && silent && !dokon && !(chip->reg_test0 & 16)); + + int level2 = mute ? 0x1ff : (instantattack ? 0 : level); + + int add = 0; + int addshift = 0; + + if (exponent) + add |= (level >> 1) ^ 0xff; + if (linear) + add |= 4; + + if (exponent && (step1 || step2 || step3)) + addshift |= 256; + + if (step1) + addshift |= (add >> 2) | (exponent << 6) | (exponent << 7) | linear; + if (step2) + addshift |= (add >> 1) | (exponent << 7) | (linear << 1); + if (step3) + addshift |= (add >> 0) | (linear << 2); + + int levelnext = level2 + addshift; + + int ksl; + ksl = eg_ksltable[chip->fnum[1] >> 6]; + int ksl_hi = (ksl & 64) != 0; + + ksl = (ksl & 63) + (chip->block[1] << 3); + if (ksl_hi || (ksl & 64) != 0) + ksl = ksl & 63; + else + ksl = 0; + + static int eg_kslshift[4] = { + 31, 1, 2, 0 + }; + + ksl = (ksl << 2) >> eg_kslshift[chip->ksl[1]]; + + int ksltl = ksl + (chip->tl[1] << 2); + + int tremolo; + + if (!chip->am[1]) + tremolo = 0; + else if (chip->reg_dv) + tremolo = chip->trem_out >> 2; + else + tremolo = chip->trem_out >> 4; + + int ksltltrem = ksltl + tremolo; + int levelof = 0; + + if (ksltltrem & 0x200) + levelof = 1; + + int totallevel = level + (ksltltrem & 0x1ff); + if (totallevel & 0x200) + levelof = 1; + + int totallevelclamp = (chip->reg_test0 & 1) != 0 ? 0 : (levelof ? 0x1ff : (totallevel & 0x1ff)); + + chip->eg_out[0] = totallevelclamp; + + chip->eg_dbg[0] = chip->eg_dbg[1] >> 1; + + if ((chip->reg_test0 & 32) != 0 && !chip->eg_dbg_load_l[1]) + { + chip->eg_dbg[0] |= chip->eg_out[1]; + } + chip->eg_dbg_load_l[0] = (chip->reg_test0 & 32) != 0; + + if (chip->fsm_out[4] || chip->fsm_out[6]) + chip->eg_index[0] = 0; + else + chip->eg_index[0] = chip->eg_index[1] + 1; + + if (chip->eg_index[1] < 18) + { + int index1 = chip->eg_index[1]; + int index2 = (index1 + 17) % 18; + chip->eg_cells[index2] = (nextstate & 3) | ((levelnext & 511) << 2) | (chip->eg_timer_i << 11); + chip->eg_cells[index2 + 18] = chip->eg_cells[index1]; + chip->eg_state_o[0] = chip->eg_cells[18 + index1] & 3; + chip->eg_level_o[0] = (chip->eg_cells[18 + index1] >> 2) & 511; + chip->eg_timer_o[0] = (chip->eg_cells[18 + index1] >> 11) & 1; + } + chip->eg_state_o[2] = chip->eg_state_o[1]; + chip->eg_level_o[2] = chip->eg_level_o[1]; + chip->eg_timer_o[2] = chip->eg_timer_o[1]; + } + if (chip->clk2) + { + chip->eg_out[1] = chip->eg_out[0]; + chip->eg_dbg[1] = chip->eg_dbg[0]; + chip->eg_dbg_load_l[1] = chip->eg_dbg_load_l[0]; + + chip->eg_index[1] = chip->eg_index[0]; + chip->eg_state_o[1] = chip->eg_state_o[0]; + chip->eg_state_o[3] = chip->eg_state_o[2]; + chip->eg_level_o[1] = chip->eg_level_o[0]; + chip->eg_level_o[3] = chip->eg_level_o[2]; + chip->eg_timer_o[1] = chip->eg_timer_o[0]; + chip->eg_timer_o[3] = chip->eg_timer_o[2]; + } + + if (chip->clk1) + { + static const int pg_multi[16] = { + 1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 20, 24, 24, 30, 30 + }; + int fnum = chip->fnum[1]; + int freq; + int pg_add; + int vib_sel1 = (chip->vib_cnt[1] & 3) == 2; + int vib_sel2 = (chip->vib_cnt[1] & 1) == 1; + int vib_sh0 = chip->reg_dv && chip->vib[1] && vib_sel1; + int vib_sh1 = (chip->reg_dv && chip->vib[1] && vib_sel2) + || (!chip->reg_dv && chip->vib[1] && vib_sel1); + int vib_sh2 = !chip->reg_dv && chip->vib[1] && vib_sel2; + int vib_sign = (chip->vib_cnt[1] & 4) != 0 && chip->vib[1]; + int vib_add = 0; + int phase; + if (vib_sh0) + vib_add |= (chip->fnum[1] >> 7) & 7; + if (vib_sh1) + vib_add |= (chip->fnum[1] >> 8) & 3; + if (vib_sh2) + vib_add |= (chip->fnum[1] >> 9) & 1; + if (vib_sign) + { + vib_add ^= 1023; + } + fnum += vib_add; + fnum += vib_sign; + if (vib_sign) + fnum &= 1023; + + freq = (fnum << chip->block[1]) >> 1; + + pg_add = (freq * pg_multi[chip->multi[1]]) >> 1; + + int state = chip->eg_state_o[3]; + int dokon = state == eg_state_release && chip->keyon_comb; + + phase = ((dokon || (chip->reg_test0 & 4) != 0 || chip->reset1) ? 0 : chip->pg_phase_o[3]) + pg_add; + + if (chip->fsm_out[4] || chip->fsm_out[6]) + chip->pg_index[0] = 0; + else + chip->pg_index[0] = chip->pg_index[1] + 1; + + if (chip->pg_index[1] < 18) + { + int index1 = chip->pg_index[1]; + int index2 = (index1 + 17) % 18; + chip->pg_cells[index2] = phase; + chip->pg_cells[index2 + 18] = chip->pg_cells[index1]; + chip->pg_phase_o[0] = chip->pg_cells[18 + index1]; + } + chip->pg_phase_o[2] = chip->pg_phase_o[1]; + } + if (chip->clk2) + { + chip->pg_index[1] = chip->pg_index[0]; + chip->pg_phase_o[1] = chip->pg_phase_o[0]; + chip->pg_phase_o[3] = chip->pg_phase_o[2]; + } + + if (chip->rclk1) + { + int noise_bit; + + noise_bit = ((chip->noise_lfsr[1] >> 22) ^ (chip->noise_lfsr[1] >> 8)) & 1; + + if ((chip->noise_lfsr[1] & 0x7fffff) == 0) + noise_bit |= 1; + + noise_bit |= (chip->reg_test0 & 2) != 0; + + if (chip->reset1) + noise_bit = 0; + + chip->noise_lfsr[0] = (chip->noise_lfsr[1] << 1) | noise_bit; + } + if (chip->rclk2) + { + chip->noise_lfsr[1] = chip->noise_lfsr[0]; + } + + { + int pg_out = chip->pg_phase_o[3] >> 9; + int hh = chip->fsm_out[2] && chip->rhythm; + int sd = chip->fsm_out[3] && chip->rhythm; + int tc = chip->fsm_out[4] && chip->rhythm; + int rhy = (chip->fsm_out[2] || chip->fsm_out[3] || chip->fsm_out[4]) && chip->rhythm; + if (chip->clk1) + chip->hh_load = chip->fsm_out[2]; + if (!chip->hh_load && chip->fsm_out[2]) + { + chip->hh_bit2 = (pg_out >> 2) & 1; + chip->hh_bit3 = (pg_out >> 3) & 1; + chip->hh_bit7 = (pg_out >> 7) & 1; + chip->hh_bit8 = (pg_out >> 8) & 1; + } + if (chip->clk1) + chip->tc_load = tc; + if (!chip->tc_load && tc) + { + chip->tc_bit3 = (pg_out >> 3) & 1; + chip->tc_bit5 = (pg_out >> 5) & 1; + } + + if (chip->clk1) // opt + { + int rm_bit; + int noise = (chip->noise_lfsr[1] >> 22) & 1; + + rm_bit = (chip->hh_bit2 ^ chip->hh_bit7) + | (chip->tc_bit5 ^ chip->hh_bit3) + | (chip->tc_bit5 ^ chip->tc_bit3); + + chip->pg_out_rhy = 0; + if (!rhy) + chip->pg_out_rhy |= pg_out; + if (hh) + { + chip->pg_out_rhy |= rm_bit << 9; + if (noise ^ rm_bit) + chip->pg_out_rhy |= 0xd0; + else + chip->pg_out_rhy |= 0x34; + } + if (sd) + chip->pg_out_rhy |= (chip->hh_bit8 << 9) | ((noise ^ chip->hh_bit8) << 8); + if (tc) + chip->pg_out_rhy |= (rm_bit << 9) | 0x80; + } + + if (chip->clk1) + { + chip->pg_dbg[0] = chip->pg_dbg[1] >> 1; + + chip->pg_dbg_load_l[0] = (chip->reg_test0 & 8) != 0; + + if ((chip->reg_test0 & 8) != 0 && !chip->pg_dbg_load_l[1]) + { + chip->pg_dbg[0] |= chip->pg_phase_o[3] & 0x1ff; + chip->pg_dbg[0] |= (chip->pg_out_rhy & 0x3ff) << 9; + } + } + if (chip->clk2) + { + chip->pg_dbg_load_l[1] = chip->pg_dbg_load_l[0]; + + chip->pg_dbg[1] = chip->pg_dbg[0]; + } + } + + { + + if (chip->clk1) + { + static const int logsin[128] = { + 0x6c3, 0x58b, 0x4e4, 0x471, 0x41a, 0x3d3, 0x398, 0x365, 0x339, 0x311, 0x2ed, 0x2cd, 0x2af, 0x293, 0x279, 0x261, + 0x24b, 0x236, 0x222, 0x20f, 0x1fd, 0x1ec, 0x1dc, 0x1cd, 0x1be, 0x1b0, 0x1a2, 0x195, 0x188, 0x17c, 0x171, 0x166, + 0x15b, 0x150, 0x146, 0x13c, 0x133, 0x129, 0x121, 0x118, 0x10f, 0x107, 0x0ff, 0x0f8, 0x0f0, 0x0e9, 0x0e2, 0x0db, + 0x0d4, 0x0cd, 0x0c7, 0x0c1, 0x0bb, 0x0b5, 0x0af, 0x0a9, 0x0a4, 0x09f, 0x099, 0x094, 0x08f, 0x08a, 0x086, 0x081, + 0x07d, 0x078, 0x074, 0x070, 0x06c, 0x068, 0x064, 0x060, 0x05c, 0x059, 0x055, 0x052, 0x04e, 0x04b, 0x048, 0x045, + 0x042, 0x03f, 0x03c, 0x039, 0x037, 0x034, 0x031, 0x02f, 0x02d, 0x02a, 0x028, 0x026, 0x024, 0x022, 0x020, 0x01e, + 0x01c, 0x01a, 0x018, 0x017, 0x015, 0x014, 0x012, 0x011, 0x00f, 0x00e, 0x00d, 0x00c, 0x00a, 0x009, 0x008, 0x007, + 0x007, 0x006, 0x005, 0x004, 0x004, 0x003, 0x002, 0x002, 0x001, 0x001, 0x001, 0x001, 0x000, 0x000, 0x000, 0x000 + }; + static const int logsin_d[128] = { + 0x196, 0x07c, 0x04a, 0x035, 0x029, 0x022, 0x01d, 0x019, 0x015, 0x013, 0x012, 0x00f, 0x00e, 0x00d, 0x00d, 0x00c, + 0x00b, 0x00a, 0x00a, 0x009, 0x009, 0x009, 0x008, 0x007, 0x007, 0x007, 0x007, 0x006, 0x007, 0x006, 0x006, 0x005, + 0x005, 0x005, 0x005, 0x005, 0x004, 0x005, 0x004, 0x004, 0x005, 0x004, 0x004, 0x003, 0x004, 0x003, 0x003, 0x003, + 0x003, 0x004, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x002, 0x003, 0x003, 0x003, 0x003, 0x002, 0x002, + 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x001, 0x002, 0x002, 0x002, 0x001, + 0x001, 0x001, 0x002, 0x002, 0x001, 0x001, 0x002, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, + 0x001, 0x001, 0x001, 0x000, 0x001, 0x000, 0x001, 0x000, 0x001, 0x001, 0x000, 0x000, 0x001, 0x001, 0x001, 0x001, + 0x000, 0x000, 0x000, 0x001, 0x000, 0x000, 0x001, 0x000, 0x001, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000 + }; + static const int pow[128] = { + 0x3f5, 0x3ea, 0x3df, 0x3d4, 0x3c9, 0x3bf, 0x3b4, 0x3a9, 0x39f, 0x394, 0x38a, 0x37f, 0x375, 0x36a, 0x360, 0x356, + 0x34c, 0x342, 0x338, 0x32e, 0x324, 0x31a, 0x310, 0x306, 0x2fd, 0x2f3, 0x2e9, 0x2e0, 0x2d6, 0x2cd, 0x2c4, 0x2ba, + 0x2b1, 0x2a8, 0x29e, 0x295, 0x28c, 0x283, 0x27a, 0x271, 0x268, 0x25f, 0x257, 0x24e, 0x245, 0x23c, 0x234, 0x22b, + 0x223, 0x21a, 0x212, 0x209, 0x201, 0x1f9, 0x1f0, 0x1e8, 0x1e0, 0x1d8, 0x1d0, 0x1c8, 0x1c0, 0x1b8, 0x1b0, 0x1a8, + 0x1a0, 0x199, 0x191, 0x189, 0x181, 0x17a, 0x172, 0x16b, 0x163, 0x15c, 0x154, 0x14d, 0x146, 0x13e, 0x137, 0x130, + 0x129, 0x122, 0x11b, 0x114, 0x10c, 0x106, 0x0ff, 0x0f8, 0x0f1, 0x0ea, 0x0e3, 0x0dc, 0x0d6, 0x0cf, 0x0c8, 0x0c2, + 0x0bb, 0x0b5, 0x0ae, 0x0a8, 0x0a1, 0x09b, 0x094, 0x08e, 0x088, 0x082, 0x07b, 0x075, 0x06f, 0x069, 0x063, 0x05d, + 0x057, 0x051, 0x04b, 0x045, 0x03f, 0x039, 0x033, 0x02d, 0x028, 0x022, 0x01c, 0x016, 0x011, 0x00b, 0x006, 0x000, + }; + static const int pow_d[128] = { + 0x005, 0x005, 0x005, 0x006, 0x006, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x006, 0x005, 0x005, + 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x004, 0x005, + 0x004, 0x004, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x004, 0x004, 0x004, 0x005, 0x004, 0x005, + 0x004, 0x004, 0x004, 0x005, 0x004, 0x004, 0x005, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, + 0x004, 0x003, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x003, 0x004, 0x004, 0x004, + 0x003, 0x003, 0x003, 0x003, 0x004, 0x003, 0x003, 0x003, 0x003, 0x003, 0x004, 0x004, 0x003, 0x003, 0x004, 0x003, + 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x004, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, + 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x002, 0x003, 0x003, 0x003, 0x003, 0x003, 0x002, 0x003, + }; + int wf = chip->wf[1]; + int phase = chip->pg_out_rhy + chip->op_mod[1]; + int square = wf == 6; + int sawtooth = wf == 7; + + int phase2; + if (wf == 4 || wf == 5) + phase2 = phase << 1; + else + phase2 = phase; + phase2 &= 1023; + + if (wf == 7 ? (phase2 & 512) != 0 : (phase2 & 256) != 0) + phase2 ^= 511; + + int mute = ((phase & 512) != 0 && (wf == 1 || wf == 4 || wf == 5)) || ((phase & 256) != 0 && wf == 3); + int sign = (wf == 2 || wf == 3 || wf == 5) ? 0 : (phase2 & 512) != 0; + + int index = square ? 255 : (phase2 & 255); + + int ls = logsin[index >> 1]; + if ((index & 1) == 0) + ls += logsin_d[index >> 1]; + + chip->op_logsin[0] = ls; + chip->op_saw[0] = sawtooth; + chip->op_saw_phase[0] = phase2 & 511; + + int att = (chip->op_saw[1] ? (chip->op_saw_phase[1] << 3) : chip->op_logsin[1]) + (chip->eg_out[1] << 3); + if (att & 4096) + att = 4095; + + int pw = pow[(att >> 1) & 127]; + if ((att & 1) == 0) + pw += pow_d[(att >> 1) & 127]; + + chip->op_shift[0] = (att >> 8) & 15; + chip->op_pow[0] = pw; + + chip->op_mute[0] = (chip->op_mute[1] << 1) | mute; + chip->op_sign[0] = (chip->op_sign[1] << 1) | sign; + + int value = 0; + + if ((chip->op_mute[1] & 2) == 0) + { + value = ((chip->op_pow[1] | 0x400) << 1) >> chip->op_shift[1]; + } + + if ((chip->op_mute[1] & 2) == 0 && (chip->op_sign[1] & 2) != 0) + value ^= 8191; + + for (i = 0; i < 13; i++) + { + int bit; + chip->op_fb[0][i][0] = chip->op_fb[0][i][1] << 1; + if (chip->fsm_out[15]) + bit = (value >> i) & 1; + else + bit = (chip->op_fb[0][i][1] >> 8) & 1; + chip->op_fb[0][i][0] |= bit; + chip->op_fb[1][i][0] = chip->op_fb[1][i][1] << 1; + if (chip->fsm_out[15]) + bit = (chip->op_fb[0][i][1] >> 8) & 1; + else + bit = (chip->op_fb[1][i][1] >> 8) & 1; + chip->op_fb[1][i][0] |= bit; + chip->op_fb[2][i][0] = chip->op_fb[2][i][1] << 1; + if (chip->fsm_out[15]) + bit = (chip->op_fb[1][i][1] >> 8) & 1; + else + bit = (chip->op_fb[2][i][1] >> 8) & 1; + chip->op_fb[2][i][0] |= bit; + chip->op_fb[3][i][0] = chip->op_fb[3][i][1] << 1; + if (chip->fsm_out[15]) + bit = (chip->op_fb[2][i][1] >> 8) & 1; + else + bit = (chip->op_fb[3][i][1] >> 8) & 1; + chip->op_fb[3][i][0] |= bit; + } + + int fb1 = 0; + int fb2 = 0; + for (i = 0; i < 14; i++) + { + int j = i; + if (i == 13) + j = 12; + fb1 |= ((chip->op_fb[1][j][1] >> 5) & 1) << i; + fb2 |= ((chip->op_fb[3][j][1] >> 5) & 1) << i; + } + int fb_sum = fb1 + fb2; + fb_sum &= 16383; + if (fb_sum & 8192) + fb_sum |= ~8191; + + int mod = 0; + + if (chip->fsm_out[16] && !chip->fsm_out[14]) + mod |= value & 1023; + if (chip->fsm_out[12]) + { + if (chip->fb_l[1][1]) + { + mod |= (fb_sum >> (9 - chip->fb_l[1][1])) & 1023; + } + } + + chip->op_mod[0] = mod & 1023; + + chip->op_value = value; + } + if (chip->clk2) + { + chip->op_logsin[1] = chip->op_logsin[0]; + chip->op_saw[1] = chip->op_saw[0]; + chip->op_saw_phase[1] = chip->op_saw_phase[0]; + chip->op_shift[1] = chip->op_shift[0]; + chip->op_pow[1] = chip->op_pow[0]; + chip->op_mute[1] = chip->op_mute[0]; + chip->op_sign[1] = chip->op_sign[0]; + + for (i = 0; i < 13; i++) + { + chip->op_fb[0][i][1] = chip->op_fb[0][i][0]; + chip->op_fb[1][i][1] = chip->op_fb[1][i][0]; + chip->op_fb[2][i][1] = chip->op_fb[2][i][0]; + chip->op_fb[3][i][1] = chip->op_fb[3][i][0]; + } + chip->op_mod[1] = chip->op_mod[0]; + } + } + + { + if (chip->clk1) + { + chip->accm_load_ac_l = chip->fsm_out[6]; + chip->accm_load_bd_l = chip->fsm_out[4]; + } + chip->accm_load_ac = !chip->accm_load_ac_l && chip->fsm_out[6]; + chip->accm_load_bd = !chip->accm_load_bd_l && chip->fsm_out[4]; + + if (chip->accm_load_ac) + { + chip->accm_a_sign = (chip->accm_a[1] & 0x40000) == 0; + chip->accm_a_of = !((chip->accm_a[1] & 0x78000) == 0 || (chip->accm_a[1] & 0x78000) == 0x78000); + chip->accm_c_sign = (chip->accm_c[1] & 0x40000) == 0; + chip->accm_c_of = !((chip->accm_c[1] & 0x78000) == 0 || (chip->accm_c[1] & 0x78000) == 0x78000); + } + + if (chip->accm_load_bd) + { + chip->accm_b_sign = (chip->accm_b[1] & 0x40000) == 0; + chip->accm_b_of = !((chip->accm_b[1] & 0x78000) == 0 || (chip->accm_b[1] & 0x78000) == 0x78000); + chip->accm_d_sign = (chip->accm_d[1] & 0x40000) == 0; + chip->accm_d_of = !((chip->accm_d[1] & 0x78000) == 0 || (chip->accm_d[1] & 0x78000) == 0x78000); + } + + if (chip->clk1) + { + int value = 0; + + if (chip->fsm_out[13]) + { + if (chip->fsm_out[11]) + value = chip->op_value << 1; + else + { + value = chip->op_value; + if (chip->op_value & 0x1000) + value |= 0x2000; + } + } + if (value & 0x2000) + { + value |= 0x7c000; + } + + int sign; + + int accm_a = chip->fsm_out[6] ? 0 : chip->accm_a[1]; + accm_a += (chip->pan_l[1][1] & 1) != 0 ? value : 0; + chip->accm_a[0] = accm_a; + sign = (chip->accm_a[1] & 0x40000) == 0; + chip->accm_shift_a[0] = (chip->accm_shift_a[1] >> 1); + if (chip->fsm_out[6]) + { + chip->accm_shift_a[0] |= chip->accm_a[1] & 0x7fff; + if (sign) + chip->accm_shift_a[0] |= 0x8000; + } + + int accm_b = chip->fsm_out[4] ? 0 : chip->accm_b[1]; + accm_b += (chip->pan_l[1][1] & 2) != 0 ? value : 0; + chip->accm_b[0] = accm_b; + sign = (chip->accm_b[1] & 0x40000) == 0; + chip->accm_shift_b[0] = (chip->accm_shift_b[1] >> 1); + if (chip->fsm_out[4]) + { + chip->accm_shift_b[0] |= chip->accm_b[1] & 0x7fff; + if (sign) + chip->accm_shift_b[0] |= 0x8000; + } + + int accm_c = chip->fsm_out[6] ? 0 : chip->accm_c[1]; + accm_c += (chip->pan_l[1][1] & 4) != 0 ? value : 0; + chip->accm_c[0] = accm_c; + sign = (chip->accm_c[1] & 0x40000) == 0; + chip->accm_shift_c[0] = (chip->accm_shift_c[1] >> 1); + if (chip->fsm_out[6]) + { + chip->accm_shift_c[0] |= chip->accm_c[1] & 0x7fff; + if (sign) + chip->accm_shift_c[0] |= 0x8000; + } + + int accm_d = chip->fsm_out[4] ? 0 : chip->accm_d[1]; + accm_d += (chip->pan_l[1][1] & 8) != 0 ? value : 0; + chip->accm_d[0] = accm_d; + sign = (chip->accm_d[1] & 0x40000) == 0; + chip->accm_shift_d[0] = (chip->accm_shift_d[1] >> 1); + if (chip->fsm_out[4]) + { + chip->accm_shift_d[0] |= chip->accm_d[1] & 0x7fff; + if (sign) + chip->accm_shift_d[0] |= 0x8000; + } + } + if (chip->clk2) + { + chip->accm_a[1] = chip->accm_a[0]; + chip->accm_b[1] = chip->accm_b[0]; + chip->accm_c[1] = chip->accm_c[0]; + chip->accm_d[1] = chip->accm_d[0]; + + chip->accm_shift_a[1] = chip->accm_shift_a[0]; + chip->accm_shift_b[1] = chip->accm_shift_b[0]; + chip->accm_shift_c[1] = chip->accm_shift_c[0]; + chip->accm_shift_d[1] = chip->accm_shift_d[0]; + } + + if (chip->fsm_out[8]) + { + chip->o_doab = chip->accm_a_of ? chip->accm_a_sign : chip->accm_shift_a[1] & 1; + chip->o_docd = chip->accm_c_of ? chip->accm_c_sign : chip->accm_shift_c[1] & 1; + } + else + { + chip->o_doab = chip->accm_b_of ? chip->accm_b_sign : chip->accm_shift_b[1] & 1; + chip->o_docd = chip->accm_d_of ? chip->accm_d_sign : chip->accm_shift_d[1] & 1; + } + } + + chip->o_sy = chip->clk2; + chip->o_smpac = chip->fsm_out[10]; + chip->o_smpbd = chip->fsm_out[9]; + chip->o_irq_pull = chip->t1_status || chip->t2_status; + + if (chip->io_read) + { + chip->data_o = 0; + if (chip->t1_status || chip->t2_status) + chip->data_o |= 128; + if (chip->t1_status) + chip->data_o |= 64; + if (chip->t2_status) + chip->data_o |= 32; + chip->data_z = 0; + } + else + chip->data_z = 1; + + { + if (chip->clk1) + { + chip->ra_dbg1[0] = chip->ra_dbg1[1] >> 1; + chip->ra_dbg2[0] = chip->ra_dbg2[1] >> 1; + if ((chip->reg_test0 & 128) != 0 && !chip->ra_dbg_load[1]) + { + chip->ra_dbg1[0] |= (int64_t)chip->multi[1] << 0; + chip->ra_dbg1[0] |= (int64_t)chip->ksr[1] << 4; + chip->ra_dbg1[0] |= (int64_t)chip->egt[1] << 5; + chip->ra_dbg1[0] |= (int64_t)chip->vib[1] << 6; + chip->ra_dbg1[0] |= (int64_t)chip->am[1] << 7; + chip->ra_dbg1[0] |= (int64_t)chip->tl[1] << 8; + chip->ra_dbg1[0] |= (int64_t)chip->ksl[1] << 14; + chip->ra_dbg1[0] |= (int64_t)chip->dr[1] << 16; + chip->ra_dbg1[0] |= (int64_t)chip->ar[1] << 20; + chip->ra_dbg1[0] |= (int64_t)chip->rr[1] << 24; + chip->ra_dbg1[0] |= (int64_t)chip->sl[1] << 28; + chip->ra_dbg1[0] |= (int64_t)chip->wf[1] << 32; + chip->ra_dbg2[0] |= (int64_t)chip->fnum[1] << 0; + chip->ra_dbg2[0] |= (int64_t)chip->block[1] << 10; + chip->ra_dbg2[0] |= (int64_t)chip->keyon[1] << 13; + chip->ra_dbg2[0] |= (int64_t)chip->connect[1] << 14; + chip->ra_dbg2[0] |= (int64_t)chip->pan[1] << 15; + chip->ra_dbg2[0] |= (int64_t)chip->connect_pair[1] << 19; + chip->ra_dbg2[0] |= (int64_t)chip->fb[1] << 20; + } + chip->ra_dbg_load[0] = (chip->reg_test0 & 128) != 0; + } + if (chip->clk2) + { + chip->ra_dbg1[1] = chip->ra_dbg1[0]; + chip->ra_dbg2[1] = chip->ra_dbg2[0]; + chip->ra_dbg_load[1] = chip->ra_dbg_load[0]; + } + } + + switch (chip->reg_test1 & 7) + { + case 0: + chip->o_test = 0; + break; + case 1: + chip->o_test = (chip->ra_dbg1[1] & 1) != 0; + break; + case 2: + chip->o_test = (chip->ra_dbg2[1] & 1) != 0; + break; + case 3: + chip->o_test = (chip->pg_dbg[1] & 1) != 0; + break; + case 4: + chip->o_test = (chip->eg_dbg[1] & 1) != 0; + break; + } + +end: + + if (chip->io_write0) + chip->write0_sr = 1; + else if (chip->reset0 || chip->write0_l[1]) + chip->write0_sr = 0; + + if (chip->io_write1) + chip->write1_sr = 1; + else if (chip->reset0 || chip->write1_l[1]) + chip->write1_sr = 0; + + if (chip->clk1) + { + chip->write0_l[0] = chip->write0_sr; + chip->write0_l[2] = chip->write0_l[1]; + + chip->write1_l[0] = chip->write1_sr; + chip->write1_l[2] = chip->write1_l[1]; + } + + if (chip->mclk1) + { + chip->prescaler1_reset[0] = (chip->prescaler1_reset[1] << 1) | chip->reset1; + + if (!(chip->prescaler1_reset[1] & 2) && chip->reset1) + chip->prescaler1_cnt[0] = 0; + else + chip->prescaler1_cnt[0] = (chip->prescaler1_cnt[1] + 1) & 3; + } + + if (chip->aclk1) + { + int prescaler2_reset = !(chip->prescaler2_reset_l[1] & 2) && chip->reset1; + chip->prescaler2_reset_l[0] = (chip->prescaler2_reset_l[1] << 1) | chip->reset1; + + if (prescaler2_reset) + chip->prescaler2_cnt[0] = 0; + else + chip->prescaler2_cnt[0] = (chip->prescaler2_cnt[1] + 1) & 3; + + chip->prescaler2_l1[0] = !prescaler2_reset && (chip->prescaler2_cnt[1] & 1) == 0; + chip->prescaler2_l2 = chip->prescaler2_l1[1]; + + chip->prescaler2_l3[0] = !prescaler2_reset && (chip->prescaler2_cnt[1] & 1) != 0; + chip->prescaler2_l4 = chip->prescaler2_l3[1]; + + chip->prescaler2_l5[0] = !prescaler2_reset && chip->prescaler2_cnt[1] == 3; + + chip->prescaler2_l6[0] = !prescaler2_reset && chip->prescaler2_cnt[1] == 1; + + chip->prescaler2_l7 = (chip->prescaler2_cnt[1] & 1) == 0; + } +} diff --git a/extern/YMF262-LLE/fmopl3.h b/extern/YMF262-LLE/fmopl3.h new file mode 100644 index 000000000..8b465ee7e --- /dev/null +++ b/extern/YMF262-LLE/fmopl3.h @@ -0,0 +1,333 @@ +/* + * Copyright (C) 2023 nukeykt + * + * This file is part of YMF262-LLE. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * YMF262 emulator + * Thanks: + * John McMaster (siliconpr0n.org): + * YMF262 decap and die shot + * + */ + +#pragma once + +#include + +typedef struct +{ + int mclk; + int address; + int data_i; + int ic; + int cs; + int rd; + int wr; +} fmopl3_input_t; + +typedef struct +{ + fmopl3_input_t input; + + int mclk1; + int mclk2; + int aclk1; + int aclk2; + int clk1; + int clk2; + int rclk1; + int rclk2; + + int o_clk1; + int o_clk2; + int o_rclk1; + int o_rclk2; + int o_wrcheck; + int o_data_latch; + int o_bank_latch; + int o_reset0; + int o_ra_w1_l1; + + int prescaler1_reset[2]; + int prescaler1_cnt[2]; + + int prescaler2_reset_l[2]; + int prescaler2_cnt[2]; + int prescaler2_reset; + int prescaler2_l1[2]; + int prescaler2_l2; + int prescaler2_l3[2]; + int prescaler2_l4; + int prescaler2_l5[2]; + int prescaler2_l6[2]; + int prescaler2_l7; + + int fsm_cnt1[2]; + int fsm_cnt2[2]; + int fsm_cnt3[2]; + int fsm_cnt; + + int fsm_reset_l[2]; + int fsm_out[17]; + int fsm_l1[2]; + int fsm_l2[2]; + int fsm_l3[2]; + int fsm_l4[2]; + int fsm_l5[2]; + int fsm_l6[2]; + int fsm_l7[2]; + int fsm_l8[2]; + int fsm_l9[2]; + int fsm_l10[2]; + + int ic_latch[2]; + + int io_rd; + int io_wr; + int io_cs; + int io_a0; + int io_a1; + + int io_read; + int io_write; + int io_write0; + int io_write1; + int io_bank; + + int data_latch; + int bank_latch; + int bank_masked; + + int reg_sel1; + int reg_sel2; + int reg_sel3; + int reg_sel4; + int reg_sel5; + int reg_sel8; + int reg_selbd; + + int reg_test0; + int reg_timer1; + int reg_timer2; + int reg_notesel; + int rhythm; + int reg_rh_kon; + int reg_da; + int reg_dv; + + int reg_test1; + int reg_new; + int reg_4op; + + int reg_t1_mask; + int reg_t2_mask; + int reg_t1_start; + int reg_t2_start; + + int lfo_cnt[2]; + int vib_cnt[2]; + int t1_step; + int t2_step; + int am_step; + int vib_step; + + int rh_sel0; + int rh_sel[2]; + + int keyon_comb; + + int ra_address_latch; + int ra_address_good; + int ra_data_latch; + int ra_cnt1[2]; + int ra_cnt2[2]; + int ra_cnt3[2]; + int ra_cnt4[2]; + int ra_cnt; + int ra_rst_l[2]; + int ra_w1_l1; + int ra_w1_l2; + int ra_write; + int ra_write_a; + + int ra_multi[36]; + int ra_ksr[36]; + int ra_egt[36]; + int ra_am[36]; + int ra_vib[36]; + int ra_tl[36]; + int ra_ksl[36]; + int ra_ar[36]; + int ra_dr[36]; + int ra_sl[36]; + int ra_rr[36]; + int ra_wf[36]; + int ra_fnum[18]; + int ra_block[18]; + int ra_keyon[18]; + int ra_connect[18]; + int ra_fb[18]; + int ra_pan[18]; + int ra_connect_pair[18]; + int multi[2]; + int ksr[2]; + int egt[2]; + int am[2]; + int vib[2]; + int tl[2]; + int ksl[2]; + int ar[2]; + int dr[2]; + int sl[2]; + int rr[2]; + int wf[2]; + int fnum[2]; + int block[2]; + int keyon[2]; + int connect[2]; + int fb[2]; + int pan[2]; + int connect_pair[2]; + + int64_t ra_dbg1[2]; + int ra_dbg2[2]; + int ra_dbg_load[2]; + + int fb_l[2][2]; + int pan_l[2][2]; + + int write0_sr; + int write0_l[4]; + int write0; + + int write1_sr; + int write1_l[4]; + int write1; + + int connect_l[2]; + int connect_pair_l[2]; + + int t1_cnt[2]; + int t2_cnt[2]; + int t1_of[2]; + int t2_of[2]; + int t1_status; + int t2_status; + int timer_st_load_l; + int timer_st_load; + int t1_start; + int t2_start; + int t1_start_l[2]; + int t2_start_l[2]; + + int reset0; + int reset1; + + int pg_phase_o[4]; + int pg_dbg[2]; + int pg_dbg_load_l[2]; + int noise_lfsr[2]; + int pg_index[2]; + int pg_cells[36]; + int pg_out_rhy; + + int trem_load_l; + int trem_load; + int trem_st_load_l; + int trem_st_load; + int trem_carry[2]; + int trem_value[2]; + int trem_dir[2]; + int trem_step; + int trem_out; + int trem_of[2]; + + int eg_load_l1[2]; + int eg_load_l; + int eg_load; + + int64_t eg_timer_masked[2]; + int eg_carry[2]; + int eg_mask[2]; + int eg_subcnt[2]; + int eg_subcnt_l[2]; + int eg_sync_l[2]; + int eg_timer_low; + int eg_shift; + int eg_timer_dbg[2]; + + int eg_timer_i; + int eg_timer_o[4]; + int eg_state_o[4]; + int eg_level_o[4]; + int eg_index[2]; + int eg_cells[36]; + + int eg_out[2]; + int eg_dbg[2]; + int eg_dbg_load_l[2]; + + int hh_load; + int tc_load; + int hh_bit2; + int hh_bit3; + int hh_bit7; + int hh_bit8; + int tc_bit3; + int tc_bit5; + + int op_logsin[2]; + int op_saw[2]; + int op_saw_phase[2]; + int op_shift[2]; + int op_pow[2]; + int op_mute[2]; + int op_sign[2]; + int op_fb[4][13][2]; + int op_mod[2]; + + int op_value; + + int accm_a[2]; + int accm_b[2]; + int accm_c[2]; + int accm_d[2]; + int accm_shift_a[2]; + int accm_shift_b[2]; + int accm_shift_c[2]; + int accm_shift_d[2]; + int accm_load_ac_l; + int accm_load_ac; + int accm_load_bd_l; + int accm_load_bd; + int accm_a_of; + int accm_a_sign; + int accm_b_of; + int accm_b_sign; + int accm_c_of; + int accm_c_sign; + int accm_d_of; + int accm_d_sign; + + int o_doab; + int o_docd; + int o_sy; + int o_smpac; + int o_smpbd; + int o_irq_pull; + int o_test; + + int data_o; + int data_z; +} fmopl3_t; + diff --git a/src/engine/platform/sound/ymfm/ymfm_opl.cpp b/src/engine/platform/sound/ymfm/ymfm_opl.cpp new file mode 100644 index 000000000..bcc1144ce --- /dev/null +++ b/src/engine/platform/sound/ymfm/ymfm_opl.cpp @@ -0,0 +1,2139 @@ +// BSD 3-Clause License +// +// Copyright (c) 2021, Aaron Giles +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#include "ymfm_opl.h" +#include "ymfm_fm.ipp" + +namespace ymfm +{ + +//------------------------------------------------- +// opl_key_scale_atten - converts an +// OPL concatenated block (3 bits) and fnum +// (10 bits) into an attenuation offset; values +// here are for 6dB/octave, in 0.75dB units +// (matching total level LSB) +//------------------------------------------------- + +inline uint32_t opl_key_scale_atten(uint32_t block, uint32_t fnum_4msb) +{ + // this table uses the top 4 bits of FNUM and are the maximal values + // (for when block == 7). Values for other blocks can be computed by + // subtracting 8 for each block below 7. + static uint8_t const fnum_to_atten[16] = { 0,24,32,37,40,43,45,47,48,50,51,52,53,54,55,56 }; + int32_t result = fnum_to_atten[fnum_4msb] - 8 * (block ^ 7); + return std::max(0, result); +} + + +//********************************************************* +// OPL REGISTERS +//********************************************************* + +//------------------------------------------------- +// opl_registers_base - constructor +//------------------------------------------------- + +template +opl_registers_base::opl_registers_base() : + m_lfo_am_counter(0), + m_lfo_pm_counter(0), + m_noise_lfsr(1), + m_lfo_am(0) +{ + // create these pointers to appease overzealous compilers checking array + // bounds in unreachable code (looking at you, clang) + uint16_t *wf0 = &m_waveform[0][0]; + uint16_t *wf1 = &m_waveform[1 % WAVEFORMS][0]; + uint16_t *wf2 = &m_waveform[2 % WAVEFORMS][0]; + uint16_t *wf3 = &m_waveform[3 % WAVEFORMS][0]; + uint16_t *wf4 = &m_waveform[4 % WAVEFORMS][0]; + uint16_t *wf5 = &m_waveform[5 % WAVEFORMS][0]; + uint16_t *wf6 = &m_waveform[6 % WAVEFORMS][0]; + uint16_t *wf7 = &m_waveform[7 % WAVEFORMS][0]; + + // create the waveforms + for (uint32_t index = 0; index < WAVEFORM_LENGTH; index++) + wf0[index] = abs_sin_attenuation(index) | (bitfield(index, 9) << 15); + + if (WAVEFORMS >= 4) + { + uint16_t zeroval = wf0[0]; + for (uint32_t index = 0; index < WAVEFORM_LENGTH; index++) + { + wf1[index] = bitfield(index, 9) ? zeroval : wf0[index]; + wf2[index] = wf0[index] & 0x7fff; + wf3[index] = bitfield(index, 8) ? zeroval : (wf0[index] & 0x7fff); + if (WAVEFORMS >= 8) + { + wf4[index] = bitfield(index, 9) ? zeroval : wf0[index * 2]; + wf5[index] = bitfield(index, 9) ? zeroval : wf0[(index * 2) & 0x1ff]; + wf6[index] = bitfield(index, 9) << 15; + wf7[index] = (bitfield(index, 9) ? (index ^ 0x13ff) : index) << 3; + } + } + } + + // OPL3/OPL4 have dynamic operators, so initialize the fourop_enable value here + // since operator_map() is called right away, prior to reset() + if (Revision > 2) + m_regdata[0x104 % REGISTERS] = 0; +} + + +//------------------------------------------------- +// reset - reset to initial state +//------------------------------------------------- + +template +void opl_registers_base::reset() +{ + std::fill_n(&m_regdata[0], REGISTERS, 0); +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +template +void opl_registers_base::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_lfo_am_counter); + state.save_restore(m_lfo_pm_counter); + state.save_restore(m_lfo_am); + state.save_restore(m_noise_lfsr); + state.save_restore(m_regdata); +} + + +//------------------------------------------------- +// operator_map - return an array of operator +// indices for each channel; for OPL this is fixed +//------------------------------------------------- + +template +void opl_registers_base::operator_map(operator_mapping &dest) const +{ + if (Revision <= 2) + { + // OPL/OPL2 has a fixed map, all 2 operators + static const operator_mapping s_fixed_map = + { { + operator_list( 0, 3 ), // Channel 0 operators + operator_list( 1, 4 ), // Channel 1 operators + operator_list( 2, 5 ), // Channel 2 operators + operator_list( 6, 9 ), // Channel 3 operators + operator_list( 7, 10 ), // Channel 4 operators + operator_list( 8, 11 ), // Channel 5 operators + operator_list( 12, 15 ), // Channel 6 operators + operator_list( 13, 16 ), // Channel 7 operators + operator_list( 14, 17 ), // Channel 8 operators + } }; + dest = s_fixed_map; + } + else + { + // OPL3/OPL4 can be configured for 2 or 4 operators + uint32_t fourop = fourop_enable(); + + dest.chan[ 0] = bitfield(fourop, 0) ? operator_list( 0, 3, 6, 9 ) : operator_list( 0, 3 ); + dest.chan[ 1] = bitfield(fourop, 1) ? operator_list( 1, 4, 7, 10 ) : operator_list( 1, 4 ); + dest.chan[ 2] = bitfield(fourop, 2) ? operator_list( 2, 5, 8, 11 ) : operator_list( 2, 5 ); + dest.chan[ 3] = bitfield(fourop, 0) ? operator_list() : operator_list( 6, 9 ); + dest.chan[ 4] = bitfield(fourop, 1) ? operator_list() : operator_list( 7, 10 ); + dest.chan[ 5] = bitfield(fourop, 2) ? operator_list() : operator_list( 8, 11 ); + dest.chan[ 6] = operator_list( 12, 15 ); + dest.chan[ 7] = operator_list( 13, 16 ); + dest.chan[ 8] = operator_list( 14, 17 ); + + dest.chan[ 9] = bitfield(fourop, 3) ? operator_list( 18, 21, 24, 27 ) : operator_list( 18, 21 ); + dest.chan[10] = bitfield(fourop, 4) ? operator_list( 19, 22, 25, 28 ) : operator_list( 19, 22 ); + dest.chan[11] = bitfield(fourop, 5) ? operator_list( 20, 23, 26, 29 ) : operator_list( 20, 23 ); + dest.chan[12] = bitfield(fourop, 3) ? operator_list() : operator_list( 24, 27 ); + dest.chan[13] = bitfield(fourop, 4) ? operator_list() : operator_list( 25, 28 ); + dest.chan[14] = bitfield(fourop, 5) ? operator_list() : operator_list( 26, 29 ); + dest.chan[15] = operator_list( 30, 33 ); + dest.chan[16] = operator_list( 31, 34 ); + dest.chan[17] = operator_list( 32, 35 ); + } +} + + +//------------------------------------------------- +// write - handle writes to the register array +//------------------------------------------------- + +template +bool opl_registers_base::write(uint16_t index, uint8_t data, uint32_t &channel, uint32_t &opmask) +{ + assert(index < REGISTERS); + + // writes to the mode register with high bit set ignore the low bits + if (index == REG_MODE && bitfield(data, 7) != 0) + m_regdata[index] |= 0x80; + else + m_regdata[index] = data; + + // handle writes to the rhythm keyons + if (index == 0xbd) + { + channel = RHYTHM_CHANNEL; + opmask = bitfield(data, 5) ? bitfield(data, 0, 5) : 0; + return true; + } + + // handle writes to the channel keyons + if ((index & 0xf0) == 0xb0) + { + channel = index & 0x0f; + if (channel < 9) + { + if (IsOpl3Plus) + channel += 9 * bitfield(index, 8); + opmask = bitfield(data, 5) ? 15 : 0; + return true; + } + } + return false; +} + + +//------------------------------------------------- +// clock_noise_and_lfo - clock the noise and LFO, +// handling clock division, depth, and waveform +// computations +//------------------------------------------------- + +static int32_t opl_clock_noise_and_lfo(uint32_t &noise_lfsr, uint16_t &lfo_am_counter, uint16_t &lfo_pm_counter, uint8_t &lfo_am, uint32_t am_depth, uint32_t pm_depth) +{ + // OPL has a 23-bit noise generator for the rhythm section, running at + // a constant rate, used only for percussion input + noise_lfsr <<= 1; + noise_lfsr |= bitfield(noise_lfsr, 23) ^ bitfield(noise_lfsr, 9) ^ bitfield(noise_lfsr, 8) ^ bitfield(noise_lfsr, 1); + + // OPL has two fixed-frequency LFOs, one for AM, one for PM + + // the AM LFO has 210*64 steps; at a nominal 50kHz output, + // this equates to a period of 50000/(210*64) = 3.72Hz + uint32_t am_counter = lfo_am_counter++; + if (am_counter >= 210*64 - 1) + lfo_am_counter = 0; + + // low 8 bits are fractional; depth 0 is divided by 2, while depth 1 is times 2 + int shift = 9 - 2 * am_depth; + + // AM value is the upper bits of the value, inverted across the midpoint + // to produce a triangle + lfo_am = ((am_counter < 105*64) ? am_counter : (210*64+63 - am_counter)) >> shift; + + // the PM LFO has 8192 steps, or a nominal period of 6.1Hz + uint32_t pm_counter = lfo_pm_counter++; + + // PM LFO is broken into 8 chunks, each lasting 1024 steps; the PM value + // depends on the upper bits of FNUM, so this value is a fraction and + // sign to apply to that value, as a 1.3 value + static int8_t const pm_scale[8] = { 8, 4, 0, -4, -8, -4, 0, 4 }; + return pm_scale[bitfield(pm_counter, 10, 3)] >> (pm_depth ^ 1); +} + +template +int32_t opl_registers_base::clock_noise_and_lfo() +{ + return opl_clock_noise_and_lfo(m_noise_lfsr, m_lfo_am_counter, m_lfo_pm_counter, m_lfo_am, lfo_am_depth(), lfo_pm_depth()); +} + + +//------------------------------------------------- +// cache_operator_data - fill the operator cache +// with prefetched data; note that this code is +// also used by ymopna_registers, so it must +// handle upper channels cleanly +//------------------------------------------------- + +template +void opl_registers_base::cache_operator_data(uint32_t choffs, uint32_t opoffs, opdata_cache &cache) +{ + // set up the easy stuff + cache.waveform = &m_waveform[op_waveform(opoffs) % WAVEFORMS][0]; + + // get frequency from the channel + uint32_t block_freq = cache.block_freq = ch_block_freq(choffs); + + // compute the keycode: block_freq is: + // + // 111 | + // 21098|76543210 + // BBBFF|FFFFFFFF + // ^^^?? + // + // the 4-bit keycode uses the top 3 bits plus one of the next two bits + uint32_t keycode = bitfield(block_freq, 10, 3) << 1; + + // lowest bit is determined by note_select(); note that it is + // actually reversed from what the manual says, however + keycode |= bitfield(block_freq, 9 - note_select(), 1); + + // no detune adjustment on OPL + cache.detune = 0; + + // multiple value, as an x.1 value (0 means 0.5) + // replace the low bit with a table lookup to give 0,1,2,3,4,5,6,7,8,9,10,10,12,12,15,15 + uint32_t multiple = op_multiple(opoffs); + cache.multiple = ((multiple & 0xe) | bitfield(0xc2aa, multiple)) * 2; + if (cache.multiple == 0) + cache.multiple = 1; + + // phase step, or PHASE_STEP_DYNAMIC if PM is active; this depends on block_freq, detune, + // and multiple, so compute it after we've done those + if (op_lfo_pm_enable(opoffs) == 0) + cache.phase_step = compute_phase_step(choffs, opoffs, cache, 0); + else + cache.phase_step = opdata_cache::PHASE_STEP_DYNAMIC; + + // total level, scaled by 8 + cache.total_level = op_total_level(opoffs) << 3; + + // pre-add key scale level + uint32_t ksl = op_ksl(opoffs); + if (ksl != 0) + cache.total_level += opl_key_scale_atten(bitfield(block_freq, 10, 3), bitfield(block_freq, 6, 4)) << ksl; + + // 4-bit sustain level, but 15 means 31 so effectively 5 bits + cache.eg_sustain = op_sustain_level(opoffs); + cache.eg_sustain |= (cache.eg_sustain + 1) & 0x10; + cache.eg_sustain <<= 5; + + // determine KSR adjustment for enevlope rates + uint32_t ksrval = keycode >> (2 * (op_ksr(opoffs) ^ 1)); + cache.eg_rate[EG_ATTACK] = effective_rate(op_attack_rate(opoffs) * 4, ksrval); + cache.eg_rate[EG_DECAY] = effective_rate(op_decay_rate(opoffs) * 4, ksrval); + cache.eg_rate[EG_SUSTAIN] = op_eg_sustain(opoffs) ? 0 : effective_rate(op_release_rate(opoffs) * 4, ksrval); + cache.eg_rate[EG_RELEASE] = effective_rate(op_release_rate(opoffs) * 4, ksrval); + cache.eg_rate[EG_DEPRESS] = 0x3f; +} + + +//------------------------------------------------- +// compute_phase_step - compute the phase step +//------------------------------------------------- + +static uint32_t opl_compute_phase_step(uint32_t block_freq, uint32_t multiple, int32_t lfo_raw_pm) +{ + // OPL phase calculation has no detuning, but uses FNUMs like + // the OPN version, and computes PM a bit differently + + // extract frequency number as a 12-bit fraction + uint32_t fnum = bitfield(block_freq, 0, 10) << 2; + + // apply the phase adjustment based on the upper 3 bits + // of FNUM and the PM depth parameters + fnum += (lfo_raw_pm * bitfield(block_freq, 7, 3)) >> 1; + + // keep fnum to 12 bits + fnum &= 0xfff; + + // apply block shift to compute phase step + uint32_t block = bitfield(block_freq, 10, 3); + uint32_t phase_step = (fnum << block) >> 2; + + // apply frequency multiplier (which is cached as an x.1 value) + return (phase_step * multiple) >> 1; +} + +template +uint32_t opl_registers_base::compute_phase_step(uint32_t choffs, uint32_t opoffs, opdata_cache const &cache, int32_t lfo_raw_pm) +{ + return opl_compute_phase_step(cache.block_freq, cache.multiple, op_lfo_pm_enable(opoffs) ? lfo_raw_pm : 0); +} + + +//------------------------------------------------- +// log_keyon - log a key-on event +//------------------------------------------------- + +template +std::string opl_registers_base::log_keyon(uint32_t choffs, uint32_t opoffs) +{ + return ""; +} + + +//********************************************************* +// OPLL SPECIFICS +//********************************************************* + +//------------------------------------------------- +// opll_registers - constructor +//------------------------------------------------- + +opll_registers::opll_registers() : + m_lfo_am_counter(0), + m_lfo_pm_counter(0), + m_noise_lfsr(1), + m_lfo_am(0) +{ + // create the waveforms + for (uint32_t index = 0; index < WAVEFORM_LENGTH; index++) + m_waveform[0][index] = abs_sin_attenuation(index) | (bitfield(index, 9) << 15); + + uint16_t zeroval = m_waveform[0][0]; + for (uint32_t index = 0; index < WAVEFORM_LENGTH; index++) + m_waveform[1][index] = bitfield(index, 9) ? zeroval : m_waveform[0][index]; + + // initialize the instruments to something sane + for (uint32_t choffs = 0; choffs < CHANNELS; choffs++) + m_chinst[choffs] = &m_regdata[0]; + for (uint32_t opoffs = 0; opoffs < OPERATORS; opoffs++) + m_opinst[opoffs] = &m_regdata[bitfield(opoffs, 0)]; +} + + +//------------------------------------------------- +// reset - reset to initial state +//------------------------------------------------- + +void opll_registers::reset() +{ + std::fill_n(&m_regdata[0], REGISTERS, 0); +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void opll_registers::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_lfo_am_counter); + state.save_restore(m_lfo_pm_counter); + state.save_restore(m_lfo_am); + state.save_restore(m_noise_lfsr); + state.save_restore(m_regdata); +} + + +//------------------------------------------------- +// operator_map - return an array of operator +// indices for each channel; for OPLL this is fixed +//------------------------------------------------- + +void opll_registers::operator_map(operator_mapping &dest) const +{ + static const operator_mapping s_fixed_map = + { { + operator_list( 0, 1 ), // Channel 0 operators + operator_list( 2, 3 ), // Channel 1 operators + operator_list( 4, 5 ), // Channel 2 operators + operator_list( 6, 7 ), // Channel 3 operators + operator_list( 8, 9 ), // Channel 4 operators + operator_list( 10, 11 ), // Channel 5 operators + operator_list( 12, 13 ), // Channel 6 operators + operator_list( 14, 15 ), // Channel 7 operators + operator_list( 16, 17 ), // Channel 8 operators + } }; + dest = s_fixed_map; +} + + +//------------------------------------------------- +// write - handle writes to the register array; +// note that this code is also used by +// ymopl3_registers, so it must handle upper +// channels cleanly +//------------------------------------------------- + +bool opll_registers::write(uint16_t index, uint8_t data, uint32_t &channel, uint32_t &opmask) +{ + // unclear the address is masked down to 6 bits or if writes above + // the register top are ignored; assuming the latter for now + if (index >= REGISTERS) + return false; + + // write the new data + m_regdata[index] = data; + + // handle writes to the rhythm keyons + if (index == 0x0e) + { + channel = RHYTHM_CHANNEL; + opmask = bitfield(data, 5) ? bitfield(data, 0, 5) : 0; + return true; + } + + // handle writes to the channel keyons + if ((index & 0xf0) == 0x20) + { + channel = index & 0x0f; + if (channel < CHANNELS) + { + opmask = bitfield(data, 4) ? 3 : 0; + return true; + } + } + return false; +} + + +//------------------------------------------------- +// clock_noise_and_lfo - clock the noise and LFO, +// handling clock division, depth, and waveform +// computations +//------------------------------------------------- + +int32_t opll_registers::clock_noise_and_lfo() +{ + // implementation is the same as OPL with fixed depths + return opl_clock_noise_and_lfo(m_noise_lfsr, m_lfo_am_counter, m_lfo_pm_counter, m_lfo_am, 1, 1); +} + + +//------------------------------------------------- +// cache_operator_data - fill the operator cache +// with prefetched data; note that this code is +// also used by ymopna_registers, so it must +// handle upper channels cleanly +//------------------------------------------------- + +void opll_registers::cache_operator_data(uint32_t choffs, uint32_t opoffs, opdata_cache &cache) +{ + // first set up the instrument data + uint32_t instrument = ch_instrument(choffs); + if (rhythm_enable() && choffs >= 6) + m_chinst[choffs] = &m_instdata[8 * (15 + (choffs - 6))]; + else + m_chinst[choffs] = (instrument == 0) ? &m_regdata[0] : &m_instdata[8 * (instrument - 1)]; + m_opinst[opoffs] = m_chinst[choffs] + bitfield(opoffs, 0); + + // set up the easy stuff + cache.waveform = &m_waveform[op_waveform(opoffs) % WAVEFORMS][0]; + + // get frequency from the channel + uint32_t block_freq = cache.block_freq = ch_block_freq(choffs); + + // compute the keycode: block_freq is: + // + // 11 | + // 1098|76543210 + // BBBF|FFFFFFFF + // ^^^^ + // + // the 4-bit keycode uses the top 4 bits + uint32_t keycode = bitfield(block_freq, 8, 4); + + // no detune adjustment on OPLL + cache.detune = 0; + + // multiple value, as an x.1 value (0 means 0.5) + // replace the low bit with a table lookup to give 0,1,2,3,4,5,6,7,8,9,10,10,12,12,15,15 + uint32_t multiple = op_multiple(opoffs); + cache.multiple = ((multiple & 0xe) | bitfield(0xc2aa, multiple)) * 2; + if (cache.multiple == 0) + cache.multiple = 1; + + // phase step, or PHASE_STEP_DYNAMIC if PM is active; this depends on + // block_freq, detune, and multiple, so compute it after we've done those + if (op_lfo_pm_enable(opoffs) == 0) + cache.phase_step = compute_phase_step(choffs, opoffs, cache, 0); + else + cache.phase_step = opdata_cache::PHASE_STEP_DYNAMIC; + + // total level, scaled by 8; for non-rhythm operator 0, this is the total + // level from the instrument data; for other operators it is 4*volume + if (bitfield(opoffs, 0) == 1 || (rhythm_enable() && choffs >= 7)) + cache.total_level = op_volume(opoffs) * 4; + else + cache.total_level = ch_total_level(choffs); + cache.total_level <<= 3; + + // pre-add key scale level + uint32_t ksl = op_ksl(opoffs); + if (ksl != 0) + cache.total_level += opl_key_scale_atten(bitfield(block_freq, 9, 3), bitfield(block_freq, 5, 4)) << ksl; + + // 4-bit sustain level, but 15 means 31 so effectively 5 bits + cache.eg_sustain = op_sustain_level(opoffs); + cache.eg_sustain |= (cache.eg_sustain + 1) & 0x10; + cache.eg_sustain <<= 5; + + // The envelope diagram in the YM2413 datasheet gives values for these + // in ms from 0->48dB. The attack/decay tables give values in ms from + // 0->96dB, so to pick an equivalent decay rate, we want to find the + // closest match that is 2x the 0->48dB value: + // + // DP = 10ms (0->48db) -> 20ms (0->96db); decay of 12 gives 19.20ms + // RR = 310ms (0->48db) -> 620ms (0->96db); decay of 7 gives 613.76ms + // RS = 1200ms (0->48db) -> 2400ms (0->96db); decay of 5 gives 2455.04ms + // + // The envelope diagram for percussive sounds (eg_sustain() == 0) also uses + // "RR" to mean both the constant RR above and the Release Rate specified in + // the instrument data. In this case, Relief Pitcher's credit sound bears out + // that the Release Rate is used during sustain, and that the constant RR + // (or RS) is used during the release phase. + constexpr uint8_t DP = 12 * 4; + constexpr uint8_t RR = 7 * 4; + constexpr uint8_t RS = 5 * 4; + + // determine KSR adjustment for envelope rates + uint32_t ksrval = keycode >> (2 * (op_ksr(opoffs) ^ 1)); + cache.eg_rate[EG_DEPRESS] = DP; + cache.eg_rate[EG_ATTACK] = effective_rate(op_attack_rate(opoffs) * 4, ksrval); + cache.eg_rate[EG_DECAY] = effective_rate(op_decay_rate(opoffs) * 4, ksrval); + if (op_eg_sustain(opoffs)) + { + cache.eg_rate[EG_SUSTAIN] = 0; + cache.eg_rate[EG_RELEASE] = ch_sustain(choffs) ? RS : effective_rate(op_release_rate(opoffs) * 4, ksrval); + } + else + { + cache.eg_rate[EG_SUSTAIN] = effective_rate(op_release_rate(opoffs) * 4, ksrval); + cache.eg_rate[EG_RELEASE] = ch_sustain(choffs) ? RS : RR; + } +} + + +//------------------------------------------------- +// compute_phase_step - compute the phase step +//------------------------------------------------- + +uint32_t opll_registers::compute_phase_step(uint32_t choffs, uint32_t opoffs, opdata_cache const &cache, int32_t lfo_raw_pm) +{ + // phase step computation is the same as OPL but the block_freq has one + // more bit, which we shift in + return opl_compute_phase_step(cache.block_freq << 1, cache.multiple, op_lfo_pm_enable(opoffs) ? lfo_raw_pm : 0); +} + + +//------------------------------------------------- +// log_keyon - log a key-on event +//------------------------------------------------- + +std::string opll_registers::log_keyon(uint32_t choffs, uint32_t opoffs) +{ + return ""; +} + + + +//********************************************************* +// YM3526 +//********************************************************* + +//------------------------------------------------- +// ym3526 - constructor +//------------------------------------------------- + +ym3526::ym3526(ymfm_interface &intf) : + m_address(0), + m_fm(intf) +{ +} + + +//------------------------------------------------- +// reset - reset the system +//------------------------------------------------- + +void ym3526::reset() +{ + // reset the engines + m_fm.reset(); +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void ym3526::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_address); + m_fm.save_restore(state); +} + + +//------------------------------------------------- +// read_status - read the status register +//------------------------------------------------- + +uint8_t ym3526::read_status() +{ + return m_fm.status() | 0x06; +} + + +//------------------------------------------------- +// read - handle a read from the device +//------------------------------------------------- + +uint8_t ym3526::read(uint32_t offset) +{ + uint8_t result = 0xff; + switch (offset & 1) + { + case 0: // status port + result = read_status(); + break; + + case 1: // when A0=1 datasheet says "the data on the bus are not guaranteed" + break; + } + return result; +} + + +//------------------------------------------------- +// write_address - handle a write to the address +// register +//------------------------------------------------- + +void ym3526::write_address(uint8_t data) +{ + // YM3526 doesn't expose a busy signal, and the datasheets don't indicate + // delays, but all other OPL chips need 12 cycles for address writes + m_fm.intf().ymfm_set_busy_end(12 * m_fm.clock_prescale()); + + // just set the address + m_address = data; +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void ym3526::write_data(uint8_t data) +{ + // YM3526 doesn't expose a busy signal, and the datasheets don't indicate + // delays, but all other OPL chips need 84 cycles for data writes + m_fm.intf().ymfm_set_busy_end(84 * m_fm.clock_prescale()); + + // write to FM + m_fm.write(m_address, data); +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void ym3526::write(uint32_t offset, uint8_t data) +{ + switch (offset & 1) + { + case 0: // address port + write_address(data); + break; + + case 1: // data port + write_data(data); + break; + } +} + + +//------------------------------------------------- +// generate - generate samples of sound +//------------------------------------------------- + +void ym3526::generate(output_data *output, uint32_t numsamples) +{ + for (uint32_t samp = 0; samp < numsamples; samp++, output++) + { + // clock the system + m_fm.clock(fm_engine::ALL_CHANNELS); + + // update the FM content; mixing details for YM3526 need verification + m_fm.output(output->clear(), 1, 32767, fm_engine::ALL_CHANNELS); + + // YM3526 uses an external DAC (YM3014) with mantissa/exponent format + // convert to 10.3 floating point value and back to simulate truncation + output->roundtrip_fp(); + } +} + + + +//********************************************************* +// Y8950 +//********************************************************* + +//------------------------------------------------- +// y8950 - constructor +//------------------------------------------------- + +y8950::y8950(ymfm_interface &intf) : + m_address(0), + m_io_ddr(0), + m_fm(intf), + m_adpcm_b(intf) +{ +} + + +//------------------------------------------------- +// reset - reset the system +//------------------------------------------------- + +void y8950::reset() +{ + // reset the engines + m_fm.reset(); + m_adpcm_b.reset(); +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void y8950::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_address); + state.save_restore(m_io_ddr); + m_fm.save_restore(state); +} + + +//------------------------------------------------- +// read_status - read the status register +//------------------------------------------------- + +uint8_t y8950::read_status() +{ + // start with current FM status, masking out bits we might set + uint8_t status = m_fm.status() & ~(STATUS_ADPCM_B_EOS | STATUS_ADPCM_B_BRDY | STATUS_ADPCM_B_PLAYING); + + // insert the live ADPCM status bits + uint8_t adpcm_status = m_adpcm_b.status(); + if ((adpcm_status & adpcm_b_channel::STATUS_EOS) != 0) + status |= STATUS_ADPCM_B_EOS; + if ((adpcm_status & adpcm_b_channel::STATUS_BRDY) != 0) + status |= STATUS_ADPCM_B_BRDY; + if ((adpcm_status & adpcm_b_channel::STATUS_PLAYING) != 0) + status |= STATUS_ADPCM_B_PLAYING; + + // run it through the FM engine to handle interrupts for us + return m_fm.set_reset_status(status, ~status); +} + + +//------------------------------------------------- +// read_data - read the data port +//------------------------------------------------- + +uint8_t y8950::read_data() +{ + uint8_t result = 0xff; + switch (m_address) + { + case 0x05: // keyboard in + result = m_fm.intf().ymfm_external_read(ACCESS_IO, 1); + break; + + case 0x09: // ADPCM data + case 0x1a: + result = m_adpcm_b.read(m_address - 0x07); + break; + + case 0x19: // I/O data + result = m_fm.intf().ymfm_external_read(ACCESS_IO, 0); + break; + + default: + debug::log_unexpected_read_write("Unexpected read from Y8950 data port %02X\n", m_address); + break; + } + return result; +} + + +//------------------------------------------------- +// read - handle a read from the device +//------------------------------------------------- + +uint8_t y8950::read(uint32_t offset) +{ + uint8_t result = 0xff; + switch (offset & 1) + { + case 0: // status port + result = read_status(); + break; + + case 1: // when A0=1 datasheet says "the data on the bus are not guaranteed" + result = read_data(); + break; + } + return result; +} + + +//------------------------------------------------- +// write_address - handle a write to the address +// register +//------------------------------------------------- + +void y8950::write_address(uint8_t data) +{ + // Y8950 doesn't expose a busy signal, but it does indicate that + // address writes should be no faster than every 12 clocks + m_fm.intf().ymfm_set_busy_end(12 * m_fm.clock_prescale()); + + // just set the address + m_address = data; +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void y8950::write_data(uint8_t data) +{ + // Y8950 doesn't expose a busy signal, but it does indicate that + // data writes should be no faster than every 12 clocks for + // registers 00-1A, or every 84 clocks for other registers + m_fm.intf().ymfm_set_busy_end(((m_address <= 0x1a) ? 12 : 84) * m_fm.clock_prescale()); + + // handle special addresses + switch (m_address) + { + case 0x04: // IRQ control + m_fm.write(m_address, data); + read_status(); + break; + + case 0x06: // keyboard out + m_fm.intf().ymfm_external_write(ACCESS_IO, 1, data); + break; + + case 0x08: // split FM/ADPCM-B + m_adpcm_b.write(m_address - 0x07, (data & 0x0f) | 0x80); + m_fm.write(m_address, data & 0xc0); + break; + + case 0x07: // ADPCM-B registers + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + case 0x10: + case 0x11: + case 0x12: + case 0x15: + case 0x16: + case 0x17: + m_adpcm_b.write(m_address - 0x07, data); + break; + + case 0x18: // I/O direction + m_io_ddr = data & 0x0f; + break; + + case 0x19: // I/O data + m_fm.intf().ymfm_external_write(ACCESS_IO, 0, data & m_io_ddr); + break; + + default: // everything else to FM + m_fm.write(m_address, data); + break; + } +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void y8950::write(uint32_t offset, uint8_t data) +{ + switch (offset & 1) + { + case 0: // address port + write_address(data); + break; + + case 1: // data port + write_data(data); + break; + } +} + + +//------------------------------------------------- +// generate - generate samples of sound +//------------------------------------------------- + +void y8950::generate(output_data *output, uint32_t numsamples) +{ + for (uint32_t samp = 0; samp < numsamples; samp++, output++) + { + // clock the system + m_fm.clock(fm_engine::ALL_CHANNELS); + m_adpcm_b.clock(); + + // update the FM content; clipping need verification + m_fm.output(output->clear(), 1, 32767, fm_engine::ALL_CHANNELS); + + // mix in the ADPCM; ADPCM-B is stereo, but only one channel + // not sure how it's wired up internally + m_adpcm_b.output(*output, 3); + + // Y8950 uses an external DAC (YM3014) with mantissa/exponent format + // convert to 10.3 floating point value and back to simulate truncation + output->roundtrip_fp(); + } +} + + + +//********************************************************* +// YM3812 +//********************************************************* + +//------------------------------------------------- +// ym3812 - constructor +//------------------------------------------------- + +ym3812::ym3812(ymfm_interface &intf) : + m_address(0), + m_fm(intf) +{ +} + + +//------------------------------------------------- +// reset - reset the system +//------------------------------------------------- + +void ym3812::reset() +{ + // reset the engines + m_fm.reset(); +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void ym3812::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_address); + m_fm.save_restore(state); +} + + +//------------------------------------------------- +// read_status - read the status register +//------------------------------------------------- + +uint8_t ym3812::read_status() +{ + return m_fm.status() | 0x06; +} + + +//------------------------------------------------- +// read - handle a read from the device +//------------------------------------------------- + +uint8_t ym3812::read(uint32_t offset) +{ + uint8_t result = 0xff; + switch (offset & 1) + { + case 0: // status port + result = read_status(); + break; + + case 1: // "inhibit" according to datasheet + break; + } + return result; +} + + +//------------------------------------------------- +// write_address - handle a write to the address +// register +//------------------------------------------------- + +void ym3812::write_address(uint8_t data) +{ + // YM3812 doesn't expose a busy signal, but it does indicate that + // address writes should be no faster than every 12 clocks + m_fm.intf().ymfm_set_busy_end(12 * m_fm.clock_prescale()); + + // just set the address + m_address = data; +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void ym3812::write_data(uint8_t data) +{ + // YM3812 doesn't expose a busy signal, but it does indicate that + // data writes should be no faster than every 84 clocks + m_fm.intf().ymfm_set_busy_end(84 * m_fm.clock_prescale()); + + // write to FM + m_fm.write(m_address, data); +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void ym3812::write(uint32_t offset, uint8_t data) +{ + switch (offset & 1) + { + case 0: // address port + write_address(data); + break; + + case 1: // data port + write_data(data); + break; + } +} + + +//------------------------------------------------- +// generate - generate samples of sound +//------------------------------------------------- + +void ym3812::generate(output_data *output, uint32_t numsamples) +{ + for (uint32_t samp = 0; samp < numsamples; samp++, output++) + { + // clock the system + m_fm.clock(fm_engine::ALL_CHANNELS); + + // update the FM content; mixing details for YM3812 need verification + m_fm.output(output->clear(), 1, 32767, fm_engine::ALL_CHANNELS); + + // YM3812 uses an external DAC (YM3014) with mantissa/exponent format + // convert to 10.3 floating point value and back to simulate truncation + output->roundtrip_fp(); + } +} + + + +//********************************************************* +// YMF262 +//********************************************************* + +//------------------------------------------------- +// ymf262 - constructor +//------------------------------------------------- + +ymf262::ymf262(ymfm_interface &intf) : + m_address(0), + m_fm(intf) +{ +} + + +//------------------------------------------------- +// reset - reset the system +//------------------------------------------------- + +void ymf262::reset() +{ + // reset the engines + m_fm.reset(); +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void ymf262::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_address); + m_fm.save_restore(state); +} + + +//------------------------------------------------- +// read_status - read the status register +//------------------------------------------------- + +uint8_t ymf262::read_status() +{ + return m_fm.status(); +} + + +//------------------------------------------------- +// read - handle a read from the device +//------------------------------------------------- + +uint8_t ymf262::read(uint32_t offset) +{ + uint8_t result = 0xff; + switch (offset & 3) + { + case 0: // status port + result = read_status(); + break; + + case 1: + case 2: + case 3: + debug::log_unexpected_read_write("Unexpected read from YMF262 offset %d\n", offset & 3); + break; + } + return result; +} + + +//------------------------------------------------- +// write_address - handle a write to the address +// register +//------------------------------------------------- + +void ymf262::write_address(uint8_t data) +{ + // YMF262 doesn't expose a busy signal, but it does indicate that + // address writes should be no faster than every 32 clocks + m_fm.intf().ymfm_set_busy_end(32 * m_fm.clock_prescale()); + + // just set the address + m_address = data; +} + + +//------------------------------------------------- +// write_data - handle a write to the data +// register +//------------------------------------------------- + +void ymf262::write_data(uint8_t data) +{ + // YMF262 doesn't expose a busy signal, but it does indicate that + // data writes should be no faster than every 32 clocks + m_fm.intf().ymfm_set_busy_end(32 * m_fm.clock_prescale()); + + // write to FM + m_fm.write(m_address, data); +} + + +//------------------------------------------------- +// write_address_hi - handle a write to the upper +// address register +//------------------------------------------------- + +void ymf262::write_address_hi(uint8_t data) +{ + // YMF262 doesn't expose a busy signal, but it does indicate that + // address writes should be no faster than every 32 clocks + m_fm.intf().ymfm_set_busy_end(32 * m_fm.clock_prescale()); + + // just set the address + m_address = data | 0x100; + + // tests reveal that in compatibility mode, upper bit is masked + // except for register 0x105 + if (m_fm.regs().newflag() == 0 && m_address != 0x105) + m_address &= 0xff; +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void ymf262::write(uint32_t offset, uint8_t data) +{ + switch (offset & 3) + { + case 0: // address port + write_address(data); + break; + + case 1: // data port + write_data(data); + break; + + case 2: // address port + write_address_hi(data); + break; + + case 3: // data port + write_data(data); + break; + } +} + + +//------------------------------------------------- +// generate - generate samples of sound +//------------------------------------------------- + +void ymf262::generate(output_data *output, uint32_t numsamples) +{ + for (uint32_t samp = 0; samp < numsamples; samp++, output++) + { + // clock the system + m_fm.clock(fm_engine::ALL_CHANNELS); + + // update the FM content; mixing details for YMF262 need verification + m_fm.output(output->clear(), 0, 32767, fm_engine::ALL_CHANNELS); + + // YMF262 output is 16-bit offset serial via YAC512 DAC + output->clamp16(); + } +} + + + +//********************************************************* +// YMF289B +//********************************************************* + +// YMF289B is a YMF262 with the following changes: +// * "Power down" mode added +// * Bulk register clear added +// * Busy flag added to the status register +// * Shorter busy times +// * All registers can be read +// * Only 2 outputs exposed + +//------------------------------------------------- +// ymf289b - constructor +//------------------------------------------------- + +ymf289b::ymf289b(ymfm_interface &intf) : + m_address(0), + m_fm(intf) +{ +} + + +//------------------------------------------------- +// reset - reset the system +//------------------------------------------------- + +void ymf289b::reset() +{ + // reset the engines + m_fm.reset(); +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void ymf289b::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_address); + m_fm.save_restore(state); +} + + +//------------------------------------------------- +// read_status - read the status register +//------------------------------------------------- + +uint8_t ymf289b::read_status() +{ + uint8_t result = m_fm.status(); + + // YMF289B adds a busy flag + if (ymf289b_mode() && m_fm.intf().ymfm_is_busy()) + result |= STATUS_BUSY_FLAGS; + return result; +} + + +//------------------------------------------------- +// read_data - read the data register +//------------------------------------------------- + +uint8_t ymf289b::read_data() +{ + uint8_t result = 0xff; + + // YMF289B can read register data back + if (ymf289b_mode()) + result = m_fm.regs().read(m_address); + return result; +} + + +//------------------------------------------------- +// read - handle a read from the device +//------------------------------------------------- + +uint8_t ymf289b::read(uint32_t offset) +{ + uint8_t result = 0xff; + switch (offset & 3) + { + case 0: // status port + result = read_status(); + break; + + case 1: // data port + result = read_data(); + break; + + case 2: + case 3: + debug::log_unexpected_read_write("Unexpected read from YMF289B offset %d\n", offset & 3); + break; + } + return result; +} + + +//------------------------------------------------- +// write_address - handle a write to the address +// register +//------------------------------------------------- + +void ymf289b::write_address(uint8_t data) +{ + m_address = data; + + // count busy time + m_fm.intf().ymfm_set_busy_end(56); +} + + +//------------------------------------------------- +// write_data - handle a write to the data +// register +//------------------------------------------------- + +void ymf289b::write_data(uint8_t data) +{ + // write to FM + m_fm.write(m_address, data); + + // writes to 0x108 with the CLR flag set clear the registers + if (m_address == 0x108 && bitfield(data, 2) != 0) + m_fm.regs().reset(); + + // count busy time + m_fm.intf().ymfm_set_busy_end(56); +} + + +//------------------------------------------------- +// write_address_hi - handle a write to the upper +// address register +//------------------------------------------------- + +void ymf289b::write_address_hi(uint8_t data) +{ + // just set the address + m_address = data | 0x100; + + // tests reveal that in compatibility mode, upper bit is masked + // except for register 0x105 + if (m_fm.regs().newflag() == 0 && m_address != 0x105) + m_address &= 0xff; + + // count busy time + m_fm.intf().ymfm_set_busy_end(56); +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void ymf289b::write(uint32_t offset, uint8_t data) +{ + switch (offset & 3) + { + case 0: // address port + write_address(data); + break; + + case 1: // data port + write_data(data); + break; + + case 2: // address port + write_address_hi(data); + break; + + case 3: // data port + write_data(data); + break; + } +} + + +//------------------------------------------------- +// generate - generate samples of sound +//------------------------------------------------- + +void ymf289b::generate(output_data *output, uint32_t numsamples) +{ + for (uint32_t samp = 0; samp < numsamples; samp++, output++) + { + // clock the system + m_fm.clock(fm_engine::ALL_CHANNELS); + + // update the FM content; mixing details for YMF262 need verification + fm_engine::output_data full; + m_fm.output(full.clear(), 0, 32767, fm_engine::ALL_CHANNELS); + + // YMF278B output is 16-bit offset serial via YAC512 DAC, but + // only 2 of the 4 outputs are exposed + output->data[0] = full.data[0]; + output->data[1] = full.data[1]; + output->clamp16(); + } +} + + + +//********************************************************* +// YMF278B +//********************************************************* + +//------------------------------------------------- +// ymf278b - constructor +//------------------------------------------------- + +ymf278b::ymf278b(ymfm_interface &intf) : + m_address(0), + m_fm_pos(0), + m_load_remaining(0), + m_next_status_id(false), + m_fm(intf), + m_pcm(intf) +{ +} + + +//------------------------------------------------- +// reset - reset the system +//------------------------------------------------- + +void ymf278b::reset() +{ + // reset the engines + m_fm.reset(); + m_pcm.reset(); + + // next status read will return ID + m_next_status_id = true; +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void ymf278b::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_address); + state.save_restore(m_fm_pos); + state.save_restore(m_load_remaining); + state.save_restore(m_next_status_id); + m_fm.save_restore(state); + m_pcm.save_restore(state); +} + + +//------------------------------------------------- +// read_status - read the status register +//------------------------------------------------- + +uint8_t ymf278b::read_status() +{ + uint8_t result; + + // first status read after initialization returns a chip ID, which + // varies based on the "new" flags, indicating the mode + if (m_next_status_id) + { + if (m_fm.regs().new2flag()) + result = 0x02; + else if (m_fm.regs().newflag()) + result = 0x00; + else + result = 0x06; + m_next_status_id = false; + } + else + { + result = m_fm.status(); + if (m_fm.intf().ymfm_is_busy()) + result |= STATUS_BUSY; + if (m_load_remaining != 0) + result |= STATUS_LD; + + // if new2 flag is not set, we're in OPL2 or OPL3 mode + if (!m_fm.regs().new2flag()) + result &= ~(STATUS_BUSY | STATUS_LD); + } + return result; +} + + +//------------------------------------------------- +// write_data_pcm - handle a write to the PCM data +// register +//------------------------------------------------- + +uint8_t ymf278b::read_data_pcm() +{ + // read from PCM + if (bitfield(m_address, 9) != 0) + { + uint8_t result = m_pcm.read(m_address & 0xff); + if ((m_address & 0xff) == 0x02) + result |= 0x20; + + return result; + } + return 0; +} + + +//------------------------------------------------- +// read - handle a read from the device +//------------------------------------------------- + +uint8_t ymf278b::read(uint32_t offset) +{ + uint8_t result = 0xff; + switch (offset & 7) + { + case 0: // status port + result = read_status(); + break; + + case 5: // PCM data port + result = read_data_pcm(); + break; + + default: + debug::log_unexpected_read_write("Unexpected read from ymf278b offset %d\n", offset & 3); + break; + } + return result; +} + + +//------------------------------------------------- +// write_address - handle a write to the address +// register +//------------------------------------------------- + +void ymf278b::write_address(uint8_t data) +{ + // just set the address + m_address = data; +} + + +//------------------------------------------------- +// write_data - handle a write to the data +// register +//------------------------------------------------- + +void ymf278b::write_data(uint8_t data) +{ + // write to FM + if (bitfield(m_address, 9) == 0) + { + uint8_t old = m_fm.regs().new2flag(); + m_fm.write(m_address, data); + + // changing NEW2 from 0->1 causes the next status read to + // return the chip ID + if (old == 0 && m_fm.regs().new2flag() != 0) + m_next_status_id = true; + } + + // BUSY goes for 56 clocks on FM writes + m_fm.intf().ymfm_set_busy_end(56); +} + + +//------------------------------------------------- +// write_address_hi - handle a write to the upper +// address register +//------------------------------------------------- + +void ymf278b::write_address_hi(uint8_t data) +{ + // just set the address + m_address = data | 0x100; + + // YMF262, in compatibility mode, treats the upper bit as masked + // except for register 0x105; assuming YMF278B works the same way? + if (m_fm.regs().newflag() == 0 && m_address != 0x105) + m_address &= 0xff; +} + + +//------------------------------------------------- +// write_address_pcm - handle a write to the upper +// address register +//------------------------------------------------- + +void ymf278b::write_address_pcm(uint8_t data) +{ + // just set the address + m_address = data | 0x200; +} + + +//------------------------------------------------- +// write_data_pcm - handle a write to the PCM data +// register +//------------------------------------------------- + +void ymf278b::write_data_pcm(uint8_t data) +{ + // ignore data writes if new2 is not yet set + if (m_fm.regs().new2flag() == 0) + return; + + // write to FM + if (bitfield(m_address, 9) != 0) + { + uint8_t addr = m_address & 0xff; + m_pcm.write(addr, data); + + // writes to the waveform number cause loads to happen for "about 300usec" + // which is ~13 samples at the nominal output frequency of 44.1kHz + if (addr >= 0x08 && addr <= 0x1f) + m_load_remaining = 13; + } + + // BUSY goes for 88 clocks on PCM writes + m_fm.intf().ymfm_set_busy_end(88); +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void ymf278b::write(uint32_t offset, uint8_t data) +{ + switch (offset & 7) + { + case 0: // address port + write_address(data); + break; + + case 1: // data port + write_data(data); + break; + + case 2: // address port + write_address_hi(data); + break; + + case 3: // data port + write_data(data); + break; + + case 4: // PCM address port + write_address_pcm(data); + break; + + case 5: // PCM address port + write_data_pcm(data); + break; + + default: + debug::log_unexpected_read_write("Unexpected write to ymf278b offset %d\n", offset & 7); + break; + } +} + + +//------------------------------------------------- +// generate - generate one sample of sound +//------------------------------------------------- + +void ymf278b::generate(output_data *output, uint32_t numsamples) +{ + static const int16_t s_mix_scale[8] = { 0x7fa, 0x5a4, 0x3fd, 0x2d2, 0x1fe, 0x169, 0xff, 0 }; + int32_t const pcm_l = s_mix_scale[m_pcm.regs().mix_pcm_l()]; + int32_t const pcm_r = s_mix_scale[m_pcm.regs().mix_pcm_r()]; + int32_t const fm_l = s_mix_scale[m_pcm.regs().mix_fm_l()]; + int32_t const fm_r = s_mix_scale[m_pcm.regs().mix_fm_r()]; + for (uint32_t samp = 0; samp < numsamples; samp++, output++) + { + // clock the system + m_fm_pos += FM_EXTRA_SAMPLE_STEP; + if (m_fm_pos >= FM_EXTRA_SAMPLE_THRESH) + { + m_fm.clock(fm_engine::ALL_CHANNELS); + m_fm_pos -= FM_EXTRA_SAMPLE_THRESH; + } + m_fm.clock(fm_engine::ALL_CHANNELS); + m_pcm.clock(pcm_engine::ALL_CHANNELS); + + // update the FM content; mixing details for YMF278B need verification + fm_engine::output_data fmout; + m_fm.output(fmout.clear(), 0, 32767, fm_engine::ALL_CHANNELS); + + // update the PCM content + pcm_engine::output_data pcmout; + m_pcm.output(pcmout.clear(), pcm_engine::ALL_CHANNELS); + + // DO0 output: FM channels 2+3 only + output->data[0] = fmout.data[2]; + output->data[1] = fmout.data[3]; + + // DO1 output: wavetable channels 2+3 only + output->data[2] = pcmout.data[2]; + output->data[3] = pcmout.data[3]; + + // DO2 output: mixed FM channels 0+1 and wavetable channels 0+1 + output->data[4] = (fmout.data[0] * fm_l + pcmout.data[0] * pcm_l) >> 11; + output->data[5] = (fmout.data[1] * fm_r + pcmout.data[1] * pcm_r) >> 11; + + // YMF278B output is 16-bit 2s complement serial + output->clamp16(); + } + + // decrement the load waiting count + if (m_load_remaining > 0) + m_load_remaining -= std::min(m_load_remaining, numsamples); +} + + + +//********************************************************* +// OPLL BASE +//********************************************************* + +//------------------------------------------------- +// opll_base - constructor +//------------------------------------------------- + +opll_base::opll_base(ymfm_interface &intf, uint8_t const *instrument_data) : + m_address(0), + m_fm(intf) +{ + m_fm.regs().set_instrument_data(instrument_data); +} + + +//------------------------------------------------- +// reset - reset the system +//------------------------------------------------- + +void opll_base::reset() +{ + // reset the engines + m_fm.reset(); +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void opll_base::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_address); + m_fm.save_restore(state); +} + + +//------------------------------------------------- +// write_address - handle a write to the address +// register +//------------------------------------------------- + +void opll_base::write_address(uint8_t data) +{ + // OPLL doesn't expose a busy signal, but datasheets are pretty consistent + // in indicating that address writes should be no faster than every 12 clocks + m_fm.intf().ymfm_set_busy_end(12); + + // just set the address + m_address = data; +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void opll_base::write_data(uint8_t data) +{ + // OPLL doesn't expose a busy signal, but datasheets are pretty consistent + // in indicating that address writes should be no faster than every 84 clocks + m_fm.intf().ymfm_set_busy_end(84); + + // write to FM + m_fm.write(m_address, data); +} + + +//------------------------------------------------- +// write - handle a write to the register +// interface +//------------------------------------------------- + +void opll_base::write(uint32_t offset, uint8_t data) +{ + switch (offset & 1) + { + case 0: // address port + write_address(data); + break; + + case 1: // data port + write_data(data); + break; + } +} + + +//------------------------------------------------- +// generate - generate one sample of sound +//------------------------------------------------- + +void opll_base::generate(output_data *output, uint32_t numsamples) +{ + for (uint32_t samp = 0; samp < numsamples; samp++, output++) + { + // clock the system + m_fm.clock(fm_engine::ALL_CHANNELS); + + // update the FM content; OPLL has a built-in 9-bit DAC + m_fm.output(output->clear(), 5, 256, fm_engine::ALL_CHANNELS); + + // final output is multiplexed; we don't simulate that here except + // to average over everything + output->data[0] = (output->data[0] * 128) / 9; + output->data[1] = (output->data[1] * 128) / 9; + } +} + + + +//********************************************************* +// YM2413 +//********************************************************* + +//------------------------------------------------- +// ym2413 - constructor +//------------------------------------------------- + +ym2413::ym2413(ymfm_interface &intf, uint8_t const *instrument_data) : + opll_base(intf, (instrument_data != nullptr) ? instrument_data : s_default_instruments) +{ +}; + +// table below taken from https://github.com/plgDavid/misc/wiki/Copyright-free-OPLL(x)-ROM-patches +uint8_t const ym2413::s_default_instruments[] = +{ + //April 2015 David Viens, tweaked May 19-21th 2015 Hubert Lamontagne + 0x71, 0x61, 0x1E, 0x17, 0xEF, 0x7F, 0x00, 0x17, //Violin + 0x13, 0x41, 0x1A, 0x0D, 0xF8, 0xF7, 0x23, 0x13, //Guitar + 0x13, 0x01, 0x99, 0x00, 0xF2, 0xC4, 0x11, 0x23, //Piano + 0x31, 0x61, 0x0E, 0x07, 0x98, 0x64, 0x70, 0x27, //Flute + 0x22, 0x21, 0x1E, 0x06, 0xBF, 0x76, 0x00, 0x28, //Clarinet + 0x31, 0x22, 0x16, 0x05, 0xE0, 0x71, 0x0F, 0x18, //Oboe + 0x21, 0x61, 0x1D, 0x07, 0x82, 0x8F, 0x10, 0x07, //Trumpet + 0x23, 0x21, 0x2D, 0x14, 0xFF, 0x7F, 0x00, 0x07, //Organ + 0x41, 0x61, 0x1B, 0x06, 0x64, 0x65, 0x10, 0x17, //Horn + 0x61, 0x61, 0x0B, 0x18, 0x85, 0xFF, 0x81, 0x07, //Synthesizer + 0x13, 0x01, 0x83, 0x11, 0xFA, 0xE4, 0x10, 0x04, //Harpsichord + 0x17, 0x81, 0x23, 0x07, 0xF8, 0xF8, 0x22, 0x12, //Vibraphone + 0x61, 0x50, 0x0C, 0x05, 0xF2, 0xF5, 0x29, 0x42, //Synthesizer Bass + 0x01, 0x01, 0x54, 0x03, 0xC3, 0x92, 0x03, 0x02, //Acoustic Bass + 0x41, 0x41, 0x89, 0x03, 0xF1, 0xE5, 0x11, 0x13, //Electric Guitar + 0x01, 0x01, 0x18, 0x0F, 0xDF, 0xF8, 0x6A, 0x6D, //rhythm 1 + 0x01, 0x01, 0x00, 0x00, 0xC8, 0xD8, 0xA7, 0x48, //rhythm 2 + 0x05, 0x01, 0x00, 0x00, 0xF8, 0xAA, 0x59, 0x55 //rhythm 3 +}; + + + +//********************************************************* +// YM2423 +//********************************************************* + +//------------------------------------------------- +// ym2423 - constructor +//------------------------------------------------- + +ym2423::ym2423(ymfm_interface &intf, uint8_t const *instrument_data) : + opll_base(intf, (instrument_data != nullptr) ? instrument_data : s_default_instruments) +{ +}; + +// table below taken from https://github.com/plgDavid/misc/wiki/Copyright-free-OPLL(x)-ROM-patches +uint8_t const ym2423::s_default_instruments[] = +{ + // May 4-6 2016 Hubert Lamontagne + // Doesn't seem to have any diff between opllx-x and opllx-y + // Drums seem identical to regular opll + 0x61, 0x61, 0x1B, 0x07, 0x94, 0x5F, 0x10, 0x06, //1 Strings Saw wave with vibrato Violin + 0x93, 0xB1, 0x51, 0x04, 0xF3, 0xF2, 0x70, 0xFB, //2 Guitar Jazz GuitarPiano + 0x41, 0x21, 0x11, 0x85, 0xF2, 0xF2, 0x70, 0x75, //3 Electric Guitar Same as OPLL No.15 Synth + 0x93, 0xB2, 0x28, 0x07, 0xF3, 0xF2, 0x70, 0xB4, //4 Electric Piano 2 Slow attack, tremoloDing-a-ling + 0x72, 0x31, 0x97, 0x05, 0x51, 0x6F, 0x60, 0x09, //5 Flute Same as OPLL No.4Clarinet + 0x13, 0x30, 0x18, 0x06, 0xF7, 0xF4, 0x50, 0x85, //6 Marimba Also be used as steel drumXyophone + 0x51, 0x31, 0x1C, 0x07, 0x51, 0x71, 0x20, 0x26, //7 Trumpet Same as OPLL No.7Trumpet + 0x41, 0xF4, 0x1B, 0x07, 0x74, 0x34, 0x00, 0x06, //8 Harmonica Harmonica synth + 0x50, 0x30, 0x4D, 0x03, 0x42, 0x65, 0x20, 0x06, //9 Tuba Tuba + 0x40, 0x20, 0x10, 0x85, 0xF3, 0xF5, 0x20, 0x04, //10 Synth Brass 2 Synth sweep + 0x61, 0x61, 0x1B, 0x07, 0xC5, 0x96, 0xF3, 0xF6, //11 Short Saw Saw wave with short envelopeSynth hit + 0xF9, 0xF1, 0xDC, 0x00, 0xF5, 0xF3, 0x77, 0xF2, //12 Vibraphone Bright vibraphoneVibes + 0x60, 0xA2, 0x91, 0x03, 0x94, 0xC1, 0xF7, 0xF7, //13 Electric Guitar 2 Clean guitar with feedbackHarmonic bass + 0x30, 0x30, 0x17, 0x06, 0xF3, 0xF1, 0xB7, 0xFC, //14 Synth Bass 2Snappy bass + 0x31, 0x36, 0x0D, 0x05, 0xF2, 0xF4, 0x27, 0x9C, //15 Sitar Also be used as ShamisenBanjo + 0x01, 0x01, 0x18, 0x0F, 0xDF, 0xF8, 0x6A, 0x6D, //rhythm 1 + 0x01, 0x01, 0x00, 0x00, 0xC8, 0xD8, 0xA7, 0x48, //rhythm 2 + 0x05, 0x01, 0x00, 0x00, 0xF8, 0xAA, 0x59, 0x55 //rhythm 3 +}; + + + +//********************************************************* +// YMF281 +//********************************************************* + +//------------------------------------------------- +// ymf281 - constructor +//------------------------------------------------- + +ymf281::ymf281(ymfm_interface &intf, uint8_t const *instrument_data) : + opll_base(intf, (instrument_data != nullptr) ? instrument_data : s_default_instruments) +{ +}; + +// table below taken from https://github.com/plgDavid/misc/wiki/Copyright-free-OPLL(x)-ROM-patches +uint8_t const ymf281::s_default_instruments[] = +{ + // May 14th 2015 Hubert Lamontagne + 0x72, 0x21, 0x1A, 0x07, 0xF6, 0x64, 0x01, 0x16, // Clarinet ~~ Electric String Square wave with vibrato + 0x00, 0x10, 0x45, 0x00, 0xF6, 0x83, 0x73, 0x63, // Synth Bass ~~ Bow wow Triangular wave + 0x13, 0x01, 0x96, 0x00, 0xF1, 0xF4, 0x31, 0x23, // Piano ~~ Electric Guitar Despite of its name, same as Piano of YM2413. + 0x71, 0x21, 0x0B, 0x0F, 0xF9, 0x64, 0x70, 0x17, // Flute ~~ Organ Sine wave + 0x02, 0x21, 0x1E, 0x06, 0xF9, 0x76, 0x00, 0x28, // Square Wave ~~ Clarinet Same as ones of YM2413. + 0x00, 0x61, 0x82, 0x0E, 0xF9, 0x61, 0x20, 0x27, // Space Oboe ~~ Saxophone Saw wave with vibrato + 0x21, 0x61, 0x1B, 0x07, 0x84, 0x8F, 0x10, 0x07, // Trumpet ~~ Trumpet Same as ones of YM2413. + 0x37, 0x32, 0xCA, 0x02, 0x66, 0x64, 0x47, 0x29, // Wow Bell ~~ Street Organ Calliope + 0x41, 0x41, 0x07, 0x03, 0xF5, 0x70, 0x51, 0xF5, // Electric Guitar ~~ Synth Brass Same as Synthesizer of YM2413. + 0x36, 0x01, 0x5E, 0x07, 0xF2, 0xF3, 0xF7, 0xF7, // Vibes ~~ Electric Piano Simulate of Rhodes Piano + 0x00, 0x00, 0x18, 0x06, 0xC5, 0xF3, 0x20, 0xF2, // Bass ~~ Bass Electric bass + 0x17, 0x81, 0x25, 0x07, 0xF7, 0xF3, 0x21, 0xF7, // Vibraphone ~~ Vibraphone Same as ones of YM2413. + 0x35, 0x64, 0x00, 0x00, 0xFF, 0xF3, 0x77, 0xF5, // Vibrato Bell ~~ Chime Bell + 0x11, 0x31, 0x00, 0x07, 0xDD, 0xF3, 0xFF, 0xFB, // Click Sine ~~ Tom Tom II Tom + 0x3A, 0x21, 0x00, 0x07, 0x95, 0x84, 0x0F, 0xF5, // Noise and Tone ~~ Noise for S.E. + 0x01, 0x01, 0x18, 0x0F, 0xDF, 0xF8, 0x6A, 0x6D, //rhythm 1 + 0x01, 0x01, 0x00, 0x00, 0xC8, 0xD8, 0xA7, 0x48, //rhythm 2 + 0x05, 0x01, 0x00, 0x00, 0xF8, 0xAA, 0x59, 0x55 //rhythm 3 +}; + + + +//********************************************************* +// DS1001 +//********************************************************* + +//------------------------------------------------- +// ds1001 - constructor +//------------------------------------------------- + +ds1001::ds1001(ymfm_interface &intf, uint8_t const *instrument_data) : + opll_base(intf, (instrument_data != nullptr) ? instrument_data : s_default_instruments) +{ +}; + +// table below taken from https://github.com/plgDavid/misc/wiki/Copyright-free-OPLL(x)-ROM-patches +uint8_t const ds1001::s_default_instruments[] = +{ + // May 15th 2015 Hubert Lamontagne & David Viens + 0x03, 0x21, 0x05, 0x06, 0xC8, 0x81, 0x42, 0x27, // Buzzy Bell + 0x13, 0x41, 0x14, 0x0D, 0xF8, 0xF7, 0x23, 0x12, // Guitar + 0x31, 0x11, 0x08, 0x08, 0xFA, 0xC2, 0x28, 0x22, // Wurly + 0x31, 0x61, 0x0C, 0x07, 0xF8, 0x64, 0x60, 0x27, // Flute + 0x22, 0x21, 0x1E, 0x06, 0xFF, 0x76, 0x00, 0x28, // Clarinet + 0x02, 0x01, 0x05, 0x00, 0xAC, 0xF2, 0x03, 0x02, // Synth + 0x21, 0x61, 0x1D, 0x07, 0x82, 0x8F, 0x10, 0x07, // Trumpet + 0x23, 0x21, 0x22, 0x17, 0xFF, 0x73, 0x00, 0x17, // Organ + 0x15, 0x11, 0x25, 0x00, 0x41, 0x71, 0x00, 0xF1, // Bells + 0x95, 0x01, 0x10, 0x0F, 0xB8, 0xAA, 0x50, 0x02, // Vibes + 0x17, 0xC1, 0x5E, 0x07, 0xFA, 0xF8, 0x22, 0x12, // Vibraphone + 0x71, 0x23, 0x11, 0x06, 0x65, 0x74, 0x10, 0x16, // Tutti + 0x01, 0x02, 0xD3, 0x05, 0xF3, 0x92, 0x83, 0xF2, // Fretless + 0x61, 0x63, 0x0C, 0x00, 0xA4, 0xFF, 0x30, 0x06, // Synth Bass + 0x21, 0x62, 0x0D, 0x00, 0xA1, 0xFF, 0x50, 0x08, // Sweep + 0x01, 0x01, 0x18, 0x0F, 0xDF, 0xF8, 0x6A, 0x6D, //rhythm 1 + 0x01, 0x01, 0x00, 0x00, 0xC8, 0xD8, 0xA7, 0x48, //rhythm 2 + 0x05, 0x01, 0x00, 0x00, 0xF8, 0xAA, 0x59, 0x55 //rhythm 3 +}; + + +//********************************************************* +// EXPLICIT INSTANTIATION +//********************************************************* + +template class opl_registers_base<4>; +template class fm_engine_base>; + +} diff --git a/src/engine/platform/sound/ymfm/ymfm_opl.h b/src/engine/platform/sound/ymfm/ymfm_opl.h new file mode 100644 index 000000000..843e5b274 --- /dev/null +++ b/src/engine/platform/sound/ymfm/ymfm_opl.h @@ -0,0 +1,902 @@ +// BSD 3-Clause License +// +// Copyright (c) 2021, Aaron Giles +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#ifndef YMFM_OPL_H +#define YMFM_OPL_H + +#pragma once + +#include "ymfm.h" +#include "ymfm_adpcm.h" +#include "ymfm_fm.h" +#include "ymfm_pcm.h" + +namespace ymfm +{ + +//********************************************************* +// REGISTER CLASSES +//********************************************************* + +// ======================> opl_registers_base + +// +// OPL/OPL2/OPL3/OPL4 register map: +// +// System-wide registers: +// 01 xxxxxxxx Test register +// --x----- Enable OPL compatibility mode [OPL2 only] (1 = enable) +// 02 xxxxxxxx Timer A value (4 * OPN) +// 03 xxxxxxxx Timer B value +// 04 x------- RST +// -x------ Mask timer A +// --x----- Mask timer B +// ------x- Load timer B +// -------x Load timer A +// 08 x------- CSM mode [OPL/OPL2 only] +// -x------ Note select +// BD x------- AM depth +// -x------ PM depth +// --x----- Rhythm enable +// ---x---- Bass drum key on +// ----x--- Snare drum key on +// -----x-- Tom key on +// ------x- Top cymbal key on +// -------x High hat key on +// 101 --xxxxxx Test register 2 [OPL3 only] +// 104 --x----- Channel 6 4-operator mode [OPL3 only] +// ---x---- Channel 5 4-operator mode [OPL3 only] +// ----x--- Channel 4 4-operator mode [OPL3 only] +// -----x-- Channel 3 4-operator mode [OPL3 only] +// ------x- Channel 2 4-operator mode [OPL3 only] +// -------x Channel 1 4-operator mode [OPL3 only] +// 105 -------x New [OPL3 only] +// ------x- New2 [OPL4 only] +// +// Per-channel registers (channel in address bits 0-3) +// Note that all these apply to address+100 as well on OPL3+ +// A0-A8 xxxxxxxx F-number (low 8 bits) +// B0-B8 --x----- Key on +// ---xxx-- Block (octvate, 0-7) +// ------xx F-number (high two bits) +// C0-C8 x------- CHD output (to DO0 pin) [OPL3+ only] +// -x------ CHC output (to DO0 pin) [OPL3+ only] +// --x----- CHB output (mixed right, to DO2 pin) [OPL3+ only] +// ---x---- CHA output (mixed left, to DO2 pin) [OPL3+ only] +// ----xxx- Feedback level for operator 1 (0-7) +// -------x Operator connection algorithm +// +// Per-operator registers (operator in bits 0-5) +// Note that all these apply to address+100 as well on OPL3+ +// 20-35 x------- AM enable +// -x------ PM enable (VIB) +// --x----- EG type +// ---x---- Key scale rate +// ----xxxx Multiple value (0-15) +// 40-55 xx------ Key scale level (0-3) +// --xxxxxx Total level (0-63) +// 60-75 xxxx---- Attack rate (0-15) +// ----xxxx Decay rate (0-15) +// 80-95 xxxx---- Sustain level (0-15) +// ----xxxx Release rate (0-15) +// E0-F5 ------xx Wave select (0-3) [OPL2 only] +// -----xxx Wave select (0-7) [OPL3+ only] +// + +template +class opl_registers_base : public fm_registers_base +{ + static constexpr bool IsOpl2 = (Revision == 2); + static constexpr bool IsOpl2Plus = (Revision >= 2); + static constexpr bool IsOpl3Plus = (Revision >= 3); + static constexpr bool IsOpl4Plus = (Revision >= 4); + +public: + // constants + static constexpr uint32_t OUTPUTS = IsOpl3Plus ? 4 : 1; + static constexpr uint32_t CHANNELS = IsOpl3Plus ? 18 : 9; + static constexpr uint32_t ALL_CHANNELS = (1 << CHANNELS) - 1; + static constexpr uint32_t OPERATORS = CHANNELS * 2; + static constexpr uint32_t WAVEFORMS = IsOpl3Plus ? 8 : (IsOpl2Plus ? 4 : 1); + static constexpr uint32_t REGISTERS = IsOpl3Plus ? 0x200 : 0x100; + static constexpr uint32_t REG_MODE = 0x04; + static constexpr uint32_t DEFAULT_PRESCALE = IsOpl4Plus ? 19 : (IsOpl3Plus ? 8 : 4); + static constexpr uint32_t EG_CLOCK_DIVIDER = 1; + static constexpr uint32_t CSM_TRIGGER_MASK = ALL_CHANNELS; + static constexpr bool DYNAMIC_OPS = IsOpl3Plus; + static constexpr bool MODULATOR_DELAY = !IsOpl3Plus; + static constexpr uint8_t STATUS_TIMERA = 0x40; + static constexpr uint8_t STATUS_TIMERB = 0x20; + static constexpr uint8_t STATUS_BUSY = 0; + static constexpr uint8_t STATUS_IRQ = 0x80; + + // constructor + opl_registers_base(); + + // reset to initial state + void reset(); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // map channel number to register offset + static constexpr uint32_t channel_offset(uint32_t chnum) + { + assert(chnum < CHANNELS); + if (!IsOpl3Plus) + return chnum; + else + return (chnum % 9) + 0x100 * (chnum / 9); + } + + // map operator number to register offset + static constexpr uint32_t operator_offset(uint32_t opnum) + { + assert(opnum < OPERATORS); + if (!IsOpl3Plus) + return opnum + 2 * (opnum / 6); + else + return (opnum % 18) + 2 * ((opnum % 18) / 6) + 0x100 * (opnum / 18); + } + + // return an array of operator indices for each channel + struct operator_mapping { uint32_t chan[CHANNELS]; }; + void operator_map(operator_mapping &dest) const; + + // OPL4 apparently can read back FM registers? + uint8_t read(uint16_t index) const { return m_regdata[index]; } + + // handle writes to the register array + bool write(uint16_t index, uint8_t data, uint32_t &chan, uint32_t &opmask); + + // clock the noise and LFO, if present, returning LFO PM value + int32_t clock_noise_and_lfo(); + + // reset the LFO + void reset_lfo() { m_lfo_am_counter = m_lfo_pm_counter = 0; } + + // return the AM offset from LFO for the given channel + // on OPL this is just a fixed value + uint32_t lfo_am_offset(uint32_t choffs) const { return m_lfo_am; } + + // return LFO/noise states + uint32_t noise_state() const { return m_noise_lfsr >> 23; } + + // caching helpers + void cache_operator_data(uint32_t choffs, uint32_t opoffs, opdata_cache &cache); + + // compute the phase step, given a PM value + uint32_t compute_phase_step(uint32_t choffs, uint32_t opoffs, opdata_cache const &cache, int32_t lfo_raw_pm); + + // log a key-on event + std::string log_keyon(uint32_t choffs, uint32_t opoffs); + + // system-wide registers + uint32_t test() const { return byte(0x01, 0, 8); } + uint32_t waveform_enable() const { return IsOpl2 ? byte(0x01, 5, 1) : (IsOpl3Plus ? 1 : 0); } + uint32_t timer_a_value() const { return byte(0x02, 0, 8) * 4; } // 8->10 bits + uint32_t timer_b_value() const { return byte(0x03, 0, 8); } + uint32_t status_mask() const { return byte(0x04, 0, 8) & 0x78; } + uint32_t irq_reset() const { return byte(0x04, 7, 1); } + uint32_t reset_timer_b() const { return byte(0x04, 7, 1) | byte(0x04, 5, 1); } + uint32_t reset_timer_a() const { return byte(0x04, 7, 1) | byte(0x04, 6, 1); } + uint32_t enable_timer_b() const { return 1; } + uint32_t enable_timer_a() const { return 1; } + uint32_t load_timer_b() const { return byte(0x04, 1, 1); } + uint32_t load_timer_a() const { return byte(0x04, 0, 1); } + uint32_t csm() const { return IsOpl3Plus ? 0 : byte(0x08, 7, 1); } + uint32_t note_select() const { return byte(0x08, 6, 1); } + uint32_t lfo_am_depth() const { return byte(0xbd, 7, 1); } + uint32_t lfo_pm_depth() const { return byte(0xbd, 6, 1); } + uint32_t rhythm_enable() const { return byte(0xbd, 5, 1); } + uint32_t rhythm_keyon() const { return byte(0xbd, 4, 0); } + uint32_t newflag() const { return IsOpl3Plus ? byte(0x105, 0, 1) : 0; } + uint32_t new2flag() const { return IsOpl4Plus ? byte(0x105, 1, 1) : 0; } + uint32_t fourop_enable() const { return IsOpl3Plus ? byte(0x104, 0, 6) : 0; } + + // per-channel registers + uint32_t ch_block_freq(uint32_t choffs) const { return word(0xb0, 0, 5, 0xa0, 0, 8, choffs); } + uint32_t ch_feedback(uint32_t choffs) const { return byte(0xc0, 1, 3, choffs); } + uint32_t ch_algorithm(uint32_t choffs) const { return byte(0xc0, 0, 1, choffs) | (IsOpl3Plus ? (8 | (byte(0xc3, 0, 1, choffs) << 1)) : 0); } + uint32_t ch_output_any(uint32_t choffs) const { return newflag() ? byte(0xc0 + choffs, 4, 4) : 1; } + uint32_t ch_output_0(uint32_t choffs) const { return newflag() ? byte(0xc0 + choffs, 4, 1) : 1; } + uint32_t ch_output_1(uint32_t choffs) const { return newflag() ? byte(0xc0 + choffs, 5, 1) : (IsOpl3Plus ? 1 : 0); } + uint32_t ch_output_2(uint32_t choffs) const { return newflag() ? byte(0xc0 + choffs, 6, 1) : 0; } + uint32_t ch_output_3(uint32_t choffs) const { return newflag() ? byte(0xc0 + choffs, 7, 1) : 0; } + + // per-operator registers + uint32_t op_lfo_am_enable(uint32_t opoffs) const { return byte(0x20, 7, 1, opoffs); } + uint32_t op_lfo_pm_enable(uint32_t opoffs) const { return byte(0x20, 6, 1, opoffs); } + uint32_t op_eg_sustain(uint32_t opoffs) const { return byte(0x20, 5, 1, opoffs); } + uint32_t op_ksr(uint32_t opoffs) const { return byte(0x20, 4, 1, opoffs); } + uint32_t op_multiple(uint32_t opoffs) const { return byte(0x20, 0, 4, opoffs); } + uint32_t op_ksl(uint32_t opoffs) const { uint32_t temp = byte(0x40, 6, 2, opoffs); return bitfield(temp, 1) | (bitfield(temp, 0) << 1); } + uint32_t op_total_level(uint32_t opoffs) const { return byte(0x40, 0, 6, opoffs); } + uint32_t op_attack_rate(uint32_t opoffs) const { return byte(0x60, 4, 4, opoffs); } + uint32_t op_decay_rate(uint32_t opoffs) const { return byte(0x60, 0, 4, opoffs); } + uint32_t op_sustain_level(uint32_t opoffs) const { return byte(0x80, 4, 4, opoffs); } + uint32_t op_release_rate(uint32_t opoffs) const { return byte(0x80, 0, 4, opoffs); } + uint32_t op_waveform(uint32_t opoffs) const { return IsOpl2Plus ? byte(0xe0, 0, newflag() ? 3 : 2, opoffs) : 0; } + +protected: + // return a bitfield extracted from a byte + uint32_t byte(uint32_t offset, uint32_t start, uint32_t count, uint32_t extra_offset = 0) const + { + return bitfield(m_regdata[offset + extra_offset], start, count); + } + + // return a bitfield extracted from a pair of bytes, MSBs listed first + uint32_t word(uint32_t offset1, uint32_t start1, uint32_t count1, uint32_t offset2, uint32_t start2, uint32_t count2, uint32_t extra_offset = 0) const + { + return (byte(offset1, start1, count1, extra_offset) << count2) | byte(offset2, start2, count2, extra_offset); + } + + // helper to determine if the this channel is an active rhythm channel + bool is_rhythm(uint32_t choffs) const + { + return rhythm_enable() && (choffs >= 6 && choffs <= 8); + } + + // internal state + uint16_t m_lfo_am_counter; // LFO AM counter + uint16_t m_lfo_pm_counter; // LFO PM counter + uint32_t m_noise_lfsr; // noise LFSR state + uint8_t m_lfo_am; // current LFO AM value + uint8_t m_regdata[REGISTERS]; // register data + uint16_t m_waveform[WAVEFORMS][WAVEFORM_LENGTH]; // waveforms +}; + +using opl_registers = opl_registers_base<1>; +using opl2_registers = opl_registers_base<2>; +using opl3_registers = opl_registers_base<3>; +using opl4_registers = opl_registers_base<4>; + + + +// ======================> opll_registers + +// +// OPLL register map: +// +// System-wide registers: +// 0E --x----- Rhythm enable +// ---x---- Bass drum key on +// ----x--- Snare drum key on +// -----x-- Tom key on +// ------x- Top cymbal key on +// -------x High hat key on +// 0F xxxxxxxx Test register +// +// Per-channel registers (channel in address bits 0-3) +// 10-18 xxxxxxxx F-number (low 8 bits) +// 20-28 --x----- Sustain on +// ---x---- Key on +// --- xxx- Block (octvate, 0-7) +// -------x F-number (high bit) +// 30-38 xxxx---- Instrument selection +// ----xxxx Volume +// +// User instrument registers (for carrier, modulator operators) +// 00-01 x------- AM enable +// -x------ PM enable (VIB) +// --x----- EG type +// ---x---- Key scale rate +// ----xxxx Multiple value (0-15) +// 02 xx------ Key scale level (carrier, 0-3) +// --xxxxxx Total level (modulator, 0-63) +// 03 xx------ Key scale level (modulator, 0-3) +// ---x---- Rectified wave (carrier) +// ----x--- Rectified wave (modulator) +// -----xxx Feedback level for operator 1 (0-7) +// 04-05 xxxx---- Attack rate (0-15) +// ----xxxx Decay rate (0-15) +// 06-07 xxxx---- Sustain level (0-15) +// ----xxxx Release rate (0-15) +// +// Internal (fake) registers: +// 40-48 xxxxxxxx Current instrument base address +// 4E-5F xxxxxxxx Current instrument base address + operator slot (0/1) +// 70-FF xxxxxxxx Data for instruments (1-16 plus 3 drums) +// + +class opll_registers : public fm_registers_base +{ +public: + static constexpr uint32_t OUTPUTS = 2; + static constexpr uint32_t CHANNELS = 9; + static constexpr uint32_t ALL_CHANNELS = (1 << CHANNELS) - 1; + static constexpr uint32_t OPERATORS = CHANNELS * 2; + static constexpr uint32_t WAVEFORMS = 2; + static constexpr uint32_t REGISTERS = 0x40; + static constexpr uint32_t REG_MODE = 0x3f; + static constexpr uint32_t DEFAULT_PRESCALE = 4; + static constexpr uint32_t EG_CLOCK_DIVIDER = 1; + static constexpr uint32_t CSM_TRIGGER_MASK = 0; + static constexpr bool EG_HAS_DEPRESS = true; + static constexpr bool MODULATOR_DELAY = true; + static constexpr uint8_t STATUS_TIMERA = 0; + static constexpr uint8_t STATUS_TIMERB = 0; + static constexpr uint8_t STATUS_BUSY = 0; + static constexpr uint8_t STATUS_IRQ = 0; + + // OPLL-specific constants + static constexpr uint32_t INSTDATA_SIZE = 0x90; + + // constructor + opll_registers(); + + // reset to initial state + void reset(); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // map channel number to register offset + static constexpr uint32_t channel_offset(uint32_t chnum) + { + assert(chnum < CHANNELS); + return chnum; + } + + // map operator number to register offset + static constexpr uint32_t operator_offset(uint32_t opnum) + { + assert(opnum < OPERATORS); + return opnum; + } + + // return an array of operator indices for each channel + struct operator_mapping { uint32_t chan[CHANNELS]; }; + void operator_map(operator_mapping &dest) const; + + // read a register value + uint8_t read(uint16_t index) const { return m_regdata[index]; } + + // handle writes to the register array + bool write(uint16_t index, uint8_t data, uint32_t &chan, uint32_t &opmask); + + // clock the noise and LFO, if present, returning LFO PM value + int32_t clock_noise_and_lfo(); + + // reset the LFO + void reset_lfo() { m_lfo_am_counter = m_lfo_pm_counter = 0; } + + // return the AM offset from LFO for the given channel + // on OPL this is just a fixed value + uint32_t lfo_am_offset(uint32_t choffs) const { return m_lfo_am; } + + // return LFO/noise states + uint32_t noise_state() const { return m_noise_lfsr >> 23; } + + // caching helpers + void cache_operator_data(uint32_t choffs, uint32_t opoffs, opdata_cache &cache); + + // compute the phase step, given a PM value + uint32_t compute_phase_step(uint32_t choffs, uint32_t opoffs, opdata_cache const &cache, int32_t lfo_raw_pm); + + // log a key-on event + std::string log_keyon(uint32_t choffs, uint32_t opoffs); + + // set the instrument data + void set_instrument_data(uint8_t const *data) + { + std::copy_n(data, INSTDATA_SIZE, &m_instdata[0]); + } + + // system-wide registers + uint32_t rhythm_enable() const { return byte(0x0e, 5, 1); } + uint32_t rhythm_keyon() const { return byte(0x0e, 4, 0); } + uint32_t test() const { return byte(0x0f, 0, 8); } + uint32_t waveform_enable() const { return 1; } + uint32_t timer_a_value() const { return 0; } + uint32_t timer_b_value() const { return 0; } + uint32_t status_mask() const { return 0; } + uint32_t irq_reset() const { return 0; } + uint32_t reset_timer_b() const { return 0; } + uint32_t reset_timer_a() const { return 0; } + uint32_t enable_timer_b() const { return 0; } + uint32_t enable_timer_a() const { return 0; } + uint32_t load_timer_b() const { return 0; } + uint32_t load_timer_a() const { return 0; } + uint32_t csm() const { return 0; } + + // per-channel registers + uint32_t ch_block_freq(uint32_t choffs) const { return word(0x20, 0, 4, 0x10, 0, 8, choffs); } + uint32_t ch_sustain(uint32_t choffs) const { return byte(0x20, 5, 1, choffs); } + uint32_t ch_total_level(uint32_t choffs) const { return instchbyte(0x02, 0, 6, choffs); } + uint32_t ch_feedback(uint32_t choffs) const { return instchbyte(0x03, 0, 3, choffs); } + uint32_t ch_algorithm(uint32_t choffs) const { return 0; } + uint32_t ch_instrument(uint32_t choffs) const { return byte(0x30, 4, 4, choffs); } + uint32_t ch_output_any(uint32_t choffs) const { return 1; } + uint32_t ch_output_0(uint32_t choffs) const { return !is_rhythm(choffs); } + uint32_t ch_output_1(uint32_t choffs) const { return is_rhythm(choffs); } + uint32_t ch_output_2(uint32_t choffs) const { return 0; } + uint32_t ch_output_3(uint32_t choffs) const { return 0; } + + // per-operator registers + uint32_t op_lfo_am_enable(uint32_t opoffs) const { return instopbyte(0x00, 7, 1, opoffs); } + uint32_t op_lfo_pm_enable(uint32_t opoffs) const { return instopbyte(0x00, 6, 1, opoffs); } + uint32_t op_eg_sustain(uint32_t opoffs) const { return instopbyte(0x00, 5, 1, opoffs); } + uint32_t op_ksr(uint32_t opoffs) const { return instopbyte(0x00, 4, 1, opoffs); } + uint32_t op_multiple(uint32_t opoffs) const { return instopbyte(0x00, 0, 4, opoffs); } + uint32_t op_ksl(uint32_t opoffs) const { return instopbyte(0x02, 6, 2, opoffs); } + uint32_t op_waveform(uint32_t opoffs) const { return instchbyte(0x03, 3 + bitfield(opoffs, 0), 1, opoffs >> 1); } + uint32_t op_attack_rate(uint32_t opoffs) const { return instopbyte(0x04, 4, 4, opoffs); } + uint32_t op_decay_rate(uint32_t opoffs) const { return instopbyte(0x04, 0, 4, opoffs); } + uint32_t op_sustain_level(uint32_t opoffs) const { return instopbyte(0x06, 4, 4, opoffs); } + uint32_t op_release_rate(uint32_t opoffs) const { return instopbyte(0x06, 0, 4, opoffs); } + uint32_t op_volume(uint32_t opoffs) const { return byte(0x30, 4 * bitfield(~opoffs, 0), 4, opoffs >> 1); } + +private: + // return a bitfield extracted from a byte + uint32_t byte(uint32_t offset, uint32_t start, uint32_t count, uint32_t extra_offset = 0) const + { + return bitfield(m_regdata[offset + extra_offset], start, count); + } + + // return a bitfield extracted from a pair of bytes, MSBs listed first + uint32_t word(uint32_t offset1, uint32_t start1, uint32_t count1, uint32_t offset2, uint32_t start2, uint32_t count2, uint32_t extra_offset = 0) const + { + return (byte(offset1, start1, count1, extra_offset) << count2) | byte(offset2, start2, count2, extra_offset); + } + + // helpers to read from instrument channel/operator data + uint32_t instchbyte(uint32_t offset, uint32_t start, uint32_t count, uint32_t choffs) const { return bitfield(m_chinst[choffs][offset], start, count); } + uint32_t instopbyte(uint32_t offset, uint32_t start, uint32_t count, uint32_t opoffs) const { return bitfield(m_opinst[opoffs][offset], start, count); } + + // helper to determine if the this channel is an active rhythm channel + bool is_rhythm(uint32_t choffs) const + { + return rhythm_enable() && choffs >= 6; + } + + // internal state + uint16_t m_lfo_am_counter; // LFO AM counter + uint16_t m_lfo_pm_counter; // LFO PM counter + uint32_t m_noise_lfsr; // noise LFSR state + uint8_t m_lfo_am; // current LFO AM value + uint8_t const *m_chinst[CHANNELS]; // pointer to instrument data for each channel + uint8_t const *m_opinst[OPERATORS]; // pointer to instrument data for each operator + uint8_t m_regdata[REGISTERS]; // register data + uint8_t m_instdata[INSTDATA_SIZE]; // instrument data + uint16_t m_waveform[WAVEFORMS][WAVEFORM_LENGTH]; // waveforms +}; + + + +//********************************************************* +// OPL IMPLEMENTATION CLASSES +//********************************************************* + +// ======================> ym3526 + +class ym3526 +{ +public: + using fm_engine = fm_engine_base; + using output_data = fm_engine::output_data; + static constexpr uint32_t OUTPUTS = fm_engine::OUTPUTS; + + // constructor + ym3526(ymfm_interface &intf); + + // reset + void reset(); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // pass-through helpers + uint32_t sample_rate(uint32_t input_clock) const { return m_fm.sample_rate(input_clock); } + void invalidate_caches() { m_fm.invalidate_caches(); } + + // read access + uint8_t read_status(); + uint8_t read(uint32_t offset); + + // write access + void write_address(uint8_t data); + void write_data(uint8_t data); + void write(uint32_t offset, uint8_t data); + + // generate samples of sound + void generate(output_data *output, uint32_t numsamples = 1); +protected: + // internal state + uint8_t m_address; // address register + fm_engine m_fm; // core FM engine +}; + + +// ======================> y8950 + +class y8950 +{ +public: + using fm_engine = fm_engine_base; + using output_data = fm_engine::output_data; + static constexpr uint32_t OUTPUTS = fm_engine::OUTPUTS; + + static constexpr uint8_t STATUS_ADPCM_B_PLAYING = 0x01; + static constexpr uint8_t STATUS_ADPCM_B_BRDY = 0x08; + static constexpr uint8_t STATUS_ADPCM_B_EOS = 0x10; + static constexpr uint8_t ALL_IRQS = STATUS_ADPCM_B_BRDY | STATUS_ADPCM_B_EOS | fm_engine::STATUS_TIMERA | fm_engine::STATUS_TIMERB; + + // constructor + y8950(ymfm_interface &intf); + + // reset + void reset(); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // pass-through helpers + uint32_t sample_rate(uint32_t input_clock) const { return m_fm.sample_rate(input_clock); } + void invalidate_caches() { m_fm.invalidate_caches(); } + + // read access + uint8_t read_status(); + uint8_t read_data(); + uint8_t read(uint32_t offset); + + // write access + void write_address(uint8_t data); + void write_data(uint8_t data); + void write(uint32_t offset, uint8_t data); + + // generate samples of sound + void generate(output_data *output, uint32_t numsamples = 1); + +protected: + // internal state + uint8_t m_address; // address register + uint8_t m_io_ddr; // data direction register for I/O + fm_engine m_fm; // core FM engine + adpcm_b_engine m_adpcm_b; // ADPCM-B engine +}; + + + +//********************************************************* +// OPL2 IMPLEMENTATION CLASSES +//********************************************************* + +// ======================> ym3812 + +class ym3812 +{ +public: + using fm_engine = fm_engine_base; + using output_data = fm_engine::output_data; + static constexpr uint32_t OUTPUTS = fm_engine::OUTPUTS; + + // constructor + ym3812(ymfm_interface &intf); + + // reset + void reset(); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // pass-through helpers + uint32_t sample_rate(uint32_t input_clock) const { return m_fm.sample_rate(input_clock); } + void invalidate_caches() { m_fm.invalidate_caches(); } + + // read access + uint8_t read_status(); + uint8_t read(uint32_t offset); + + // write access + void write_address(uint8_t data); + void write_data(uint8_t data); + void write(uint32_t offset, uint8_t data); + + // generate samples of sound + void generate(output_data *output, uint32_t numsamples = 1); + +protected: + // internal state + uint8_t m_address; // address register + fm_engine m_fm; // core FM engine +}; + + + +//********************************************************* +// OPL3 IMPLEMENTATION CLASSES +//********************************************************* + +// ======================> ymf262 + +class ymf262 +{ +public: + using fm_engine = fm_engine_base; + using output_data = fm_engine::output_data; + static constexpr uint32_t OUTPUTS = fm_engine::OUTPUTS; + + // constructor + ymf262(ymfm_interface &intf); + + // reset + void reset(); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // pass-through helpers + uint32_t sample_rate(uint32_t input_clock) const { return m_fm.sample_rate(input_clock); } + void invalidate_caches() { m_fm.invalidate_caches(); } + + // read access + uint8_t read_status(); + uint8_t read(uint32_t offset); + + // write access + void write_address(uint8_t data); + void write_data(uint8_t data); + void write_address_hi(uint8_t data); + void write(uint32_t offset, uint8_t data); + + // generate samples of sound + void generate(output_data *output, uint32_t numsamples = 1); + +protected: + // internal state + uint16_t m_address; // address register + fm_engine m_fm; // core FM engine +}; + + +// ======================> ymf289b + +class ymf289b +{ + static constexpr uint8_t STATUS_BUSY_FLAGS = 0x05; + +public: + using fm_engine = fm_engine_base; + using output_data = fm_engine::output_data; + static constexpr uint32_t OUTPUTS = 2; + + // constructor + ymf289b(ymfm_interface &intf); + + // reset + void reset(); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // pass-through helpers + uint32_t sample_rate(uint32_t input_clock) const { return m_fm.sample_rate(input_clock); } + void invalidate_caches() { m_fm.invalidate_caches(); } + + // read access + uint8_t read_status(); + uint8_t read_data(); + uint8_t read(uint32_t offset); + + // write access + void write_address(uint8_t data); + void write_data(uint8_t data); + void write_address_hi(uint8_t data); + void write(uint32_t offset, uint8_t data); + + // generate samples of sound + void generate(output_data *output, uint32_t numsamples = 1); + +protected: + // internal helpers + bool ymf289b_mode() { return ((m_fm.regs().read(0x105) & 0x04) != 0); } + + // internal state + uint16_t m_address; // address register + fm_engine m_fm; // core FM engine +}; + + + +//********************************************************* +// OPL4 IMPLEMENTATION CLASSES +//********************************************************* + +// ======================> ymf278b + +class ymf278b +{ + // Using the nominal datasheet frequency of 33.868MHz, the output of the + // chip will be clock/768 = 44.1kHz. However, the FM engine is clocked + // internally at clock/(19*36), or 49.515kHz, so the FM output needs to + // be downsampled. We treat this as needing to clock the FM engine an + // extra tick every few samples. The exact ratio is 768/(19*36) or + // 768/684 = 192/171. So if we always clock the FM once, we'll have + // 192/171 - 1 = 21/171 left. Thus we count 21 for each sample and when + // it gets above 171, we tick an extra time. + static constexpr uint32_t FM_EXTRA_SAMPLE_THRESH = 171; + static constexpr uint32_t FM_EXTRA_SAMPLE_STEP = 192 - FM_EXTRA_SAMPLE_THRESH; + +public: + using fm_engine = fm_engine_base; + static constexpr uint32_t OUTPUTS = 6; + using output_data = ymfm_output; + + static constexpr uint8_t STATUS_BUSY = 0x01; + static constexpr uint8_t STATUS_LD = 0x02; + + // constructor + ymf278b(ymfm_interface &intf); + + // reset + void reset(); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // pass-through helpers + uint32_t sample_rate(uint32_t input_clock) const { return input_clock / 768; } + void invalidate_caches() { m_fm.invalidate_caches(); } + + // read access + uint8_t read_status(); + uint8_t read_data_pcm(); + uint8_t read(uint32_t offset); + + // write access + void write_address(uint8_t data); + void write_data(uint8_t data); + void write_address_hi(uint8_t data); + void write_address_pcm(uint8_t data); + void write_data_pcm(uint8_t data); + void write(uint32_t offset, uint8_t data); + + // generate samples of sound + void generate(output_data *output, uint32_t numsamples = 1); + +protected: + // internal state + uint16_t m_address; // address register + uint32_t m_fm_pos; // FM resampling position + uint32_t m_load_remaining; // how many more samples until LD flag clears + bool m_next_status_id; // flag to track which status ID to return + fm_engine m_fm; // core FM engine + pcm_engine m_pcm; // core PCM engine +}; + + + +//********************************************************* +// OPLL IMPLEMENTATION CLASSES +//********************************************************* + +// ======================> opll_base + +class opll_base +{ +public: + using fm_engine = fm_engine_base; + using output_data = fm_engine::output_data; + static constexpr uint32_t OUTPUTS = fm_engine::OUTPUTS; + + // constructor + opll_base(ymfm_interface &intf, uint8_t const *data); + + // configuration + void set_instrument_data(uint8_t const *data) { m_fm.regs().set_instrument_data(data); } + + // reset + void reset(); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // pass-through helpers + uint32_t sample_rate(uint32_t input_clock) const { return m_fm.sample_rate(input_clock); } + void invalidate_caches() { m_fm.invalidate_caches(); } + + // read access -- doesn't really have any, but provide these for consistency + uint8_t read_status() { return 0x00; } + uint8_t read(uint32_t offset) { return 0x00; } + + // write access + void write_address(uint8_t data); + void write_data(uint8_t data); + void write(uint32_t offset, uint8_t data); + + // generate samples of sound + void generate(output_data *output, uint32_t numsamples = 1); + +protected: + // internal state + uint8_t m_address; // address register + fm_engine m_fm; // core FM engine +}; + + +// ======================> ym2413 + +class ym2413 : public opll_base +{ +public: + // constructor + ym2413(ymfm_interface &intf, uint8_t const *instrument_data = nullptr); + +private: + // internal state + static uint8_t const s_default_instruments[]; +}; + + +// ======================> ym2413 + +class ym2423 : public opll_base +{ +public: + // constructor + ym2423(ymfm_interface &intf, uint8_t const *instrument_data = nullptr); + +private: + // internal state + static uint8_t const s_default_instruments[]; +}; + + +// ======================> ymf281 + +class ymf281 : public opll_base +{ +public: + // constructor + ymf281(ymfm_interface &intf, uint8_t const *instrument_data = nullptr); + +private: + // internal state + static uint8_t const s_default_instruments[]; +}; + + +// ======================> ds1001 + +class ds1001 : public opll_base +{ +public: + // constructor + ds1001(ymfm_interface &intf, uint8_t const *instrument_data = nullptr); + +private: + // internal state + static uint8_t const s_default_instruments[]; +}; + +} + +#endif // YMFM_OPL_H diff --git a/src/engine/platform/sound/ymfm/ymfm_pcm.cpp b/src/engine/platform/sound/ymfm/ymfm_pcm.cpp new file mode 100644 index 000000000..34417490c --- /dev/null +++ b/src/engine/platform/sound/ymfm/ymfm_pcm.cpp @@ -0,0 +1,714 @@ +// BSD 3-Clause License +// +// Copyright (c) 2021, Aaron Giles +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#include "ymfm_pcm.h" +#include "ymfm_fm.h" +#include "ymfm_fm.ipp" + +namespace ymfm +{ + +//********************************************************* +// PCM REGISTERS +//********************************************************* + +//------------------------------------------------- +// reset - reset the register state +//------------------------------------------------- + +void pcm_registers::reset() +{ + std::fill_n(&m_regdata[0], REGISTERS, 0); + m_regdata[0xf8] = 0x1b; +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void pcm_registers::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_regdata); +} + + +//------------------------------------------------- +// cache_channel_data - update the cache with +// data from the registers +//------------------------------------------------- + +void pcm_registers::cache_channel_data(uint32_t choffs, pcm_cache &cache) +{ + // compute step from octave and fnumber; the math here implies + // a .18 fraction but .16 should be perfectly fine + int32_t octave = int8_t(ch_octave(choffs) << 4) >> 4; + uint32_t fnum = ch_fnumber(choffs); + cache.step = ((0x400 | fnum) << (octave + 7)) >> 2; + + // total level is computed as a .10 value for interpolation + cache.total_level = ch_total_level(choffs) << 10; + + // compute panning values in terms of envelope attenuation + int32_t panpot = int8_t(ch_panpot(choffs) << 4) >> 4; + if (panpot >= 0) + { + cache.pan_left = (panpot == 7) ? 0x3ff : 0x20 * panpot; + cache.pan_right = 0; + } + else if (panpot >= -7) + { + cache.pan_left = 0; + cache.pan_right = (panpot == -7) ? 0x3ff : -0x20 * panpot; + } + else + cache.pan_left = cache.pan_right = 0x3ff; + + // determine the LFO stepping value; this how much to add to a running + // x.18 value for the LFO; steps were derived from frequencies in the + // manual and come out very close with these values + static const uint8_t s_lfo_steps[8] = { 1, 12, 19, 25, 31, 35, 37, 42 }; + cache.lfo_step = s_lfo_steps[ch_lfo_speed(choffs)]; + + // AM LFO depth values, derived from the manual; note each has at most + // 2 bits to make the "multiply" easy in hardware + static const uint8_t s_am_depth[8] = { 0, 0x14, 0x20, 0x28, 0x30, 0x40, 0x50, 0x80 }; + cache.am_depth = s_am_depth[ch_am_depth(choffs)]; + + // PM LFO depth values; these are converted from the manual's cents values + // into f-numbers; the computations come out quite cleanly so pretty sure + // these are correct + static const uint8_t s_pm_depth[8] = { 0, 2, 3, 4, 6, 12, 24, 48 }; + cache.pm_depth = s_pm_depth[ch_vibrato(choffs)]; + + // 4-bit sustain level, but 15 means 31 so effectively 5 bits + cache.eg_sustain = ch_sustain_level(choffs); + cache.eg_sustain |= (cache.eg_sustain + 1) & 0x10; + cache.eg_sustain <<= 5; + + // compute the key scaling correction factor; 15 means don't do any correction + int32_t correction = ch_rate_correction(choffs); + if (correction == 15) + correction = 0; + else + correction = (octave + correction) * 2 + bitfield(fnum, 9); + + // compute the envelope generator rates + cache.eg_rate[EG_ATTACK] = effective_rate(ch_attack_rate(choffs), correction); + cache.eg_rate[EG_DECAY] = effective_rate(ch_decay_rate(choffs), correction); + cache.eg_rate[EG_SUSTAIN] = effective_rate(ch_sustain_rate(choffs), correction); + cache.eg_rate[EG_RELEASE] = effective_rate(ch_release_rate(choffs), correction); + cache.eg_rate[EG_REVERB] = 5; + + // if damping is on, override some things; essentially decay at a hardcoded + // rate of 48 until -12db (0x80), then at maximum rate for the rest + if (ch_damp(choffs) != 0) + { + cache.eg_rate[EG_DECAY] = 48; + cache.eg_rate[EG_SUSTAIN] = 63; + cache.eg_rate[EG_RELEASE] = 63; + cache.eg_sustain = 0x80; + } +} + + +//------------------------------------------------- +// effective_rate - return the effective rate, +// clamping and applying corrections as needed +//------------------------------------------------- + +uint32_t pcm_registers::effective_rate(uint32_t raw, uint32_t correction) +{ + // raw rates of 0 and 15 just pin to min/max + if (raw == 0) + return 0; + if (raw == 15) + return 63; + + // otherwise add the correction and clamp to range + return clamp(raw * 4 + correction, 0, 63); +} + + + +//********************************************************* +// PCM CHANNEL +//********************************************************* + +//------------------------------------------------- +// pcm_channel - constructor +//------------------------------------------------- + +pcm_channel::pcm_channel(pcm_engine &owner, uint32_t choffs) : + m_choffs(choffs), + m_baseaddr(0), + m_endpos(0), + m_looppos(0), + m_curpos(0), + m_nextpos(0), + m_lfo_counter(0), + m_eg_state(EG_RELEASE), + m_env_attenuation(0x3ff), + m_total_level(0x7f << 10), + m_format(0), + m_key_state(0), + m_regs(owner.regs()), + m_owner(owner) +{ +} + + +//------------------------------------------------- +// reset - reset the channel state +//------------------------------------------------- + +void pcm_channel::reset() +{ + m_baseaddr = 0; + m_endpos = 0; + m_looppos = 0; + m_curpos = 0; + m_nextpos = 0; + m_lfo_counter = 0; + m_eg_state = EG_RELEASE; + m_env_attenuation = 0x3ff; + m_total_level = 0x7f << 10; + m_format = 0; + m_key_state = 0; +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void pcm_channel::save_restore(ymfm_saved_state &state) +{ + state.save_restore(m_baseaddr); + state.save_restore(m_endpos); + state.save_restore(m_looppos); + state.save_restore(m_curpos); + state.save_restore(m_nextpos); + state.save_restore(m_lfo_counter); + state.save_restore(m_eg_state); + state.save_restore(m_env_attenuation); + state.save_restore(m_total_level); + state.save_restore(m_format); + state.save_restore(m_key_state); +} + + +//------------------------------------------------- +// prepare - prepare for clocking +//------------------------------------------------- + +bool pcm_channel::prepare() +{ + // cache the data + m_regs.cache_channel_data(m_choffs, m_cache); + + // clock the key state + if ((m_key_state & KEY_PENDING) != 0) + { + uint8_t oldstate = m_key_state; + m_key_state = (m_key_state >> 1) & KEY_ON; + if (((oldstate ^ m_key_state) & KEY_ON) != 0) + { + if ((m_key_state & KEY_ON) != 0) + start_attack(); + else + start_release(); + } + } + + // set the total level directly if not interpolating + if (m_regs.ch_level_direct(m_choffs)) + m_total_level = m_cache.total_level; + + // we're active until we're quiet after the release + return (m_eg_state < EG_RELEASE || m_env_attenuation < EG_QUIET); +} + + +//------------------------------------------------- +// clock - master clocking function +//------------------------------------------------- + +void pcm_channel::clock(uint32_t env_counter) +{ + // clock the LFO, which is an x.18 value incremented based on the + // LFO speed value + m_lfo_counter += m_cache.lfo_step; + + // clock the envelope + clock_envelope(env_counter); + + // determine the step after applying vibrato + uint32_t step = m_cache.step; + if (m_cache.pm_depth != 0) + { + // shift the LFO by 1/4 cycle for PM so that it starts at 0 + uint32_t lfo_shifted = m_lfo_counter + (1 << 16); + int32_t lfo_value = bitfield(lfo_shifted, 10, 7); + if (bitfield(lfo_shifted, 17) != 0) + lfo_value ^= 0x7f; + lfo_value -= 0x40; + step += (lfo_value * int32_t(m_cache.pm_depth)) >> 7; + } + + // advance the sample step and loop as needed + m_curpos = m_nextpos; + m_nextpos = m_curpos + step; + if (m_nextpos >= m_endpos) + m_nextpos += m_looppos - m_endpos; + + // interpolate total level if needed + if (m_total_level != m_cache.total_level) + { + // max->min volume takes 156.4ms, or pretty close to 19/1024 per 44.1kHz sample + // min->max volume is half that, so advance by 38/1024 per sample + if (m_total_level < m_cache.total_level) + m_total_level = std::min(m_total_level + 19, m_cache.total_level); + else + m_total_level = std::max(m_total_level - 38, m_cache.total_level); + } +} + + +//------------------------------------------------- +// output - return the computed output value, with +// panning applied +//------------------------------------------------- + +void pcm_channel::output(output_data &output) const +{ + // early out if the envelope is effectively off + uint32_t envelope = m_env_attenuation; + if (envelope > EG_QUIET) + return; + + // add in LFO AM modulation + if (m_cache.am_depth != 0) + { + uint32_t lfo_value = bitfield(m_lfo_counter, 10, 7); + if (bitfield(m_lfo_counter, 17) != 0) + lfo_value ^= 0x7f; + envelope += (lfo_value * m_cache.am_depth) >> 7; + } + + // add in the current interpolated total level value, which is a .10 + // value shifted left by 2 + envelope += m_total_level >> 8; + + // add in panning effect and clamp + uint32_t lenv = std::min(envelope + m_cache.pan_left, 0x3ff); + uint32_t renv = std::min(envelope + m_cache.pan_right, 0x3ff); + + // convert to volume as a .11 fraction + int32_t lvol = attenuation_to_volume(lenv << 2); + int32_t rvol = attenuation_to_volume(renv << 2); + + // fetch current sample and add + int16_t sample = fetch_sample(); + uint32_t outnum = m_regs.ch_output_channel(m_choffs) * 2; + output.data[outnum + 0] += (lvol * sample) >> 15; + output.data[outnum + 1] += (rvol * sample) >> 15; +} + + +//------------------------------------------------- +// keyonoff - signal key on/off +//------------------------------------------------- + +void pcm_channel::keyonoff(bool on) +{ + // mark the key state as pending + m_key_state |= KEY_PENDING | (on ? KEY_PENDING_ON : 0); + + // don't log masked channels + if ((m_key_state & (KEY_PENDING_ON | KEY_ON)) == KEY_PENDING_ON && ((debug::GLOBAL_PCM_CHANNEL_MASK >> m_choffs) & 1) != 0) + { + debug::log_keyon("KeyOn PCM-%02d: num=%3d oct=%2d fnum=%03X level=%02X%c ADSR=%X/%X/%X/%X SL=%X", + m_choffs, + m_regs.ch_wave_table_num(m_choffs), + int8_t(m_regs.ch_octave(m_choffs) << 4) >> 4, + m_regs.ch_fnumber(m_choffs), + m_regs.ch_total_level(m_choffs), + m_regs.ch_level_direct(m_choffs) ? '!' : '/', + m_regs.ch_attack_rate(m_choffs), + m_regs.ch_decay_rate(m_choffs), + m_regs.ch_sustain_rate(m_choffs), + m_regs.ch_release_rate(m_choffs), + m_regs.ch_sustain_level(m_choffs)); + + if (m_regs.ch_rate_correction(m_choffs) != 15) + debug::log_keyon(" RC=%X", m_regs.ch_rate_correction(m_choffs)); + + if (m_regs.ch_pseudo_reverb(m_choffs) != 0) + debug::log_keyon(" %s", "REV"); + if (m_regs.ch_damp(m_choffs) != 0) + debug::log_keyon(" %s", "DAMP"); + + if (m_regs.ch_vibrato(m_choffs) != 0 || m_regs.ch_am_depth(m_choffs) != 0) + { + if (m_regs.ch_vibrato(m_choffs) != 0) + debug::log_keyon(" VIB=%d", m_regs.ch_vibrato(m_choffs)); + if (m_regs.ch_am_depth(m_choffs) != 0) + debug::log_keyon(" AM=%d", m_regs.ch_am_depth(m_choffs)); + debug::log_keyon(" LFO=%d", m_regs.ch_lfo_speed(m_choffs)); + } + debug::log_keyon("%s", "\n"); + } +} + + +//------------------------------------------------- +// load_wavetable - load a wavetable by fetching +// its data from external memory +//------------------------------------------------- + +void pcm_channel::load_wavetable() +{ + // determine the address of the wave table header + uint32_t wavnum = m_regs.ch_wave_table_num(m_choffs); + uint32_t wavheader = 12 * wavnum; + + // above 384 it may be in a different bank + if (wavnum >= 384) + { + uint32_t bank = m_regs.wave_table_header(); + if (bank != 0) + wavheader = 512*1024 * bank + (wavnum - 384) * 12; + } + + // fetch the 22-bit base address and 2-bit format + uint8_t byte = read_pcm(wavheader + 0); + m_format = bitfield(byte, 6, 2); + m_baseaddr = bitfield(byte, 0, 6) << 16; + m_baseaddr |= read_pcm(wavheader + 1) << 8; + m_baseaddr |= read_pcm(wavheader + 2) << 0; + + // fetch the 16-bit loop position + m_looppos = read_pcm(wavheader + 3) << 8; + m_looppos |= read_pcm(wavheader + 4); + m_looppos <<= 16; + + // fetch the 16-bit end position, which is stored as a negative value + // for some reason that is unclear + m_endpos = read_pcm(wavheader + 5) << 8; + m_endpos |= read_pcm(wavheader + 6); + m_endpos = -int32_t(m_endpos) << 16; + + // remaining data values set registers + m_owner.write(0x80 + m_choffs, read_pcm(wavheader + 7)); + m_owner.write(0x98 + m_choffs, read_pcm(wavheader + 8)); + m_owner.write(0xb0 + m_choffs, read_pcm(wavheader + 9)); + m_owner.write(0xc8 + m_choffs, read_pcm(wavheader + 10)); + m_owner.write(0xe0 + m_choffs, read_pcm(wavheader + 11)); + + // reset the envelope so we don't continue playing mid-sample from previous key ons + m_env_attenuation = 0x3ff; +} + + +//------------------------------------------------- +// read_pcm - read a byte from the external PCM +// memory interface +//------------------------------------------------- + +uint8_t pcm_channel::read_pcm(uint32_t address) const +{ + return m_owner.intf().ymfm_external_read(ACCESS_PCM, address); +} + + +//------------------------------------------------- +// start_attack - start the attack phase +//------------------------------------------------- + +void pcm_channel::start_attack() +{ + // don't change anything if already in attack state + if (m_eg_state == EG_ATTACK) + return; + m_eg_state = EG_ATTACK; + + // reset the LFO if requested + if (m_regs.ch_lfo_reset(m_choffs)) + m_lfo_counter = 0; + + // if the attack rate == 63 then immediately go to max attenuation + if (m_cache.eg_rate[EG_ATTACK] == 63) + m_env_attenuation = 0; + + // reset the positions + m_curpos = m_nextpos = 0; +} + + +//------------------------------------------------- +// start_release - start the release phase +//------------------------------------------------- + +void pcm_channel::start_release() +{ + // don't change anything if already in release or reverb state + if (m_eg_state >= EG_RELEASE) + return; + m_eg_state = EG_RELEASE; +} + + +//------------------------------------------------- +// clock_envelope - clock the envelope generator +//------------------------------------------------- + +void pcm_channel::clock_envelope(uint32_t env_counter) +{ + // handle attack->decay transitions + if (m_eg_state == EG_ATTACK && m_env_attenuation == 0) + m_eg_state = EG_DECAY; + + // handle decay->sustain transitions + if (m_eg_state == EG_DECAY && m_env_attenuation >= m_cache.eg_sustain) + m_eg_state = EG_SUSTAIN; + + // fetch the appropriate 6-bit rate value from the cache + uint32_t rate = m_cache.eg_rate[m_eg_state]; + + // compute the rate shift value; this is the shift needed to + // apply to the env_counter such that it becomes a 5.11 fixed + // point number + uint32_t rate_shift = rate >> 2; + env_counter <<= rate_shift; + + // see if the fractional part is 0; if not, it's not time to clock + if (bitfield(env_counter, 0, 11) != 0) + return; + + // determine the increment based on the non-fractional part of env_counter + uint32_t relevant_bits = bitfield(env_counter, (rate_shift <= 11) ? 11 : rate_shift, 3); + uint32_t increment = attenuation_increment(rate, relevant_bits); + + // attack is the only one that increases + if (m_eg_state == EG_ATTACK) + m_env_attenuation += (~m_env_attenuation * increment) >> 4; + + // all other cases are similar + else + { + // apply the increment + m_env_attenuation += increment; + + // clamp the final attenuation + if (m_env_attenuation >= 0x400) + m_env_attenuation = 0x3ff; + + // transition to reverb at -18dB if enabled + if (m_env_attenuation >= 0xc0 && m_eg_state < EG_REVERB && m_regs.ch_pseudo_reverb(m_choffs)) + m_eg_state = EG_REVERB; + } +} + + +//------------------------------------------------- +// fetch_sample - fetch a sample at the current +// position +//------------------------------------------------- + +int16_t pcm_channel::fetch_sample() const +{ + uint32_t addr = m_baseaddr; + uint32_t pos = m_curpos >> 16; + + // 8-bit PCM: shift up by 8 + if (m_format == 0) + return read_pcm(addr + pos) << 8; + + // 16-bit PCM: assemble from 2 halves + if (m_format == 2) + { + addr += pos * 2; + return (read_pcm(addr) << 8) | read_pcm(addr + 1); + } + + // 12-bit PCM: assemble out of half of 3 bytes + addr += (pos / 2) * 3; + if ((pos & 1) == 0) + return (read_pcm(addr + 0) << 8) | ((read_pcm(addr + 1) << 4) & 0xf0); + else + return (read_pcm(addr + 2) << 8) | ((read_pcm(addr + 1) << 0) & 0xf0); +} + + + +//********************************************************* +// PCM ENGINE +//********************************************************* + +//------------------------------------------------- +// pcm_engine - constructor +//------------------------------------------------- + +pcm_engine::pcm_engine(ymfm_interface &intf) : + m_intf(intf), + m_env_counter(0), + m_modified_channels(ALL_CHANNELS), + m_active_channels(ALL_CHANNELS) +{ + // create the channels + for (int chnum = 0; chnum < CHANNELS; chnum++) + m_channel[chnum] = std::make_unique(*this, chnum); +} + + +//------------------------------------------------- +// reset - reset the engine state +//------------------------------------------------- + +void pcm_engine::reset() +{ + // reset register state + m_regs.reset(); + + // reset each channel + for (auto &chan : m_channel) + chan->reset(); +} + + +//------------------------------------------------- +// save_restore - save or restore the data +//------------------------------------------------- + +void pcm_engine::save_restore(ymfm_saved_state &state) +{ + // save our data + state.save_restore(m_env_counter); + + // save channel state + for (int chnum = 0; chnum < CHANNELS; chnum++) + m_channel[chnum]->save_restore(state); +} + + +//------------------------------------------------- +// clock - master clocking function +//------------------------------------------------- + +void pcm_engine::clock(uint32_t chanmask) +{ + // if something was modified, prepare + // also prepare every 4k samples to catch ending notes + if (m_modified_channels != 0 || m_prepare_count++ >= 4096) + { + // call each channel to prepare + m_active_channels = 0; + for (int chnum = 0; chnum < CHANNELS; chnum++) + if (bitfield(chanmask, chnum)) + if (m_channel[chnum]->prepare()) + m_active_channels |= 1 << chnum; + + // reset the modified channels and prepare count + m_modified_channels = m_prepare_count = 0; + } + + // increment the envelope counter; the envelope generator + // only clocks every other sample in order to make the PCM + // envelopes line up with the FM envelopes (after taking into + // account the different FM sampling rate) + m_env_counter++; + + // now update the state of all the channels and operators + for (int chnum = 0; chnum < CHANNELS; chnum++) + if (bitfield(chanmask, chnum)) + m_channel[chnum]->clock(m_env_counter >> 1); +} + + +//------------------------------------------------- +// update - master update function +//------------------------------------------------- + +void pcm_engine::output(output_data &output, uint32_t chanmask) +{ + // mask out some channels for debug purposes + chanmask &= debug::GLOBAL_PCM_CHANNEL_MASK; + + // compute the output of each channel + for (int chnum = 0; chnum < CHANNELS; chnum++) + if (bitfield(chanmask, chnum)) + m_channel[chnum]->output(output); +} + + +//------------------------------------------------- +// read - handle reads from the PCM registers +//------------------------------------------------- + +uint8_t pcm_engine::read(uint32_t regnum) +{ + // handle reads from the data register + if (regnum == 0x06 && m_regs.memory_access_mode() != 0) + return m_intf.ymfm_external_read(ACCESS_PCM, m_regs.memory_address_autoinc()); + + return m_regs.read(regnum); +} + + +//------------------------------------------------- +// write - handle writes to the PCM registers +//------------------------------------------------- + +void pcm_engine::write(uint32_t regnum, uint8_t data) +{ + // handle reads to the data register + if (regnum == 0x06 && m_regs.memory_access_mode() != 0) + { + m_intf.ymfm_external_write(ACCESS_PCM, m_regs.memory_address_autoinc(), data); + return; + } + + // for now just mark all channels as modified + m_modified_channels = ALL_CHANNELS; + + // most writes are passive, consumed only when needed + m_regs.write(regnum, data); + + // however, process keyons immediately + if (regnum >= 0x68 && regnum <= 0x7f) + m_channel[regnum - 0x68]->keyonoff(bitfield(data, 7)); + + // and also wavetable writes + else if (regnum >= 0x08 && regnum <= 0x1f) + m_channel[regnum - 0x08]->load_wavetable(); +} + +} diff --git a/src/engine/platform/sound/ymfm/ymfm_pcm.h b/src/engine/platform/sound/ymfm/ymfm_pcm.h new file mode 100644 index 000000000..b471fa611 --- /dev/null +++ b/src/engine/platform/sound/ymfm/ymfm_pcm.h @@ -0,0 +1,347 @@ +// BSD 3-Clause License +// +// Copyright (c) 2021, Aaron Giles +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#ifndef YMFM_PCM_H +#define YMFM_PCM_H + +#pragma once + +#include "ymfm.h" + +namespace ymfm +{ + +/* +Note to self: Sega "Multi-PCM" is almost identical to this + +28 channels + +Writes: +00 = data reg, causes write +01 = target slot = data - (data / 8) +02 = address (clamped to 7) + +Slot data (registers with ADSR/KSR seem to be inaccessible): +0: xxxx---- panpot +1: xxxxxxxx wavetable low +2: xxxxxx-- pitch low + -------x wavetable high +3: xxxx---- octave + ----xxxx pitch hi +4: x------- key on +5: xxxxxxx- total level + -------x level direct (0=interpolate) +6: --xxx--- LFO frequency + -----xxx PM sensitivity +7: -----xxx AM sensitivity + +Sample data: ++00: start hi ++01: start mid ++02: start low ++03: loop hi ++04: loop low ++05: -end hi ++06: -end low ++07: vibrato (reg 6) ++08: attack/decay ++09: sustain level/rate ++0A: ksr/release ++0B: LFO amplitude (reg 7) + +*/ + +//********************************************************* +// INTERFACE CLASSES +//********************************************************* + +class pcm_engine; + + +// ======================> pcm_cache + +// this class holds data that is computed once at the start of clocking +// and remains static during subsequent sound generation +struct pcm_cache +{ + uint32_t step; // sample position step, as a .16 value + uint32_t total_level; // target total level, as a .10 value + uint32_t pan_left; // left panning attenuation + uint32_t pan_right; // right panning attenuation + uint32_t eg_sustain; // sustain level, shifted up to envelope values + uint8_t eg_rate[EG_STATES]; // envelope rate, including KSR + uint8_t lfo_step; // stepping value for LFO + uint8_t am_depth; // scale value for AM LFO + uint8_t pm_depth; // scale value for PM LFO +}; + + +// ======================> pcm_registers + +// +// PCM register map: +// +// System-wide registers: +// 00-01 xxxxxxxx LSI Test +// 02 -------x Memory access mode (0=sound gen, 1=read/write) +// ------x- Memory type (0=ROM, 1=ROM+SRAM) +// ---xxx-- Wave table header +// xxx----- Device ID (=1 for YMF278B) +// 03 --xxxxxx Memory address high +// 04 xxxxxxxx Memory address mid +// 05 xxxxxxxx Memory address low +// 06 xxxxxxxx Memory data +// F8 --xxx--- Mix control (FM_R) +// -----xxx Mix control (FM_L) +// F9 --xxx--- Mix control (PCM_R) +// -----xxx Mix control (PCM_L) +// +// Channel-specific registers: +// 08-1F xxxxxxxx Wave table number low +// 20-37 -------x Wave table number high +// xxxxxxx- F-number low +// 38-4F -----xxx F-number high +// ----x--- Pseudo-reverb +// xxxx---- Octave +// 50-67 xxxxxxx- Total level +// -------x Level direct +// 68-7F x------- Key on +// -x------ Damp +// --x----- LFO reset +// ---x---- Output channel +// ----xxxx Panpot +// 80-97 --xxx--- LFO speed +// -----xxx Vibrato +// 98-AF xxxx---- Attack rate +// ----xxxx Decay rate +// B0-C7 xxxx---- Sustain level +// ----xxxx Sustain rate +// C8-DF xxxx---- Rate correction +// ----xxxx Release rate +// E0-F7 -----xxx AM depth + +class pcm_registers +{ +public: + // constants + static constexpr uint32_t OUTPUTS = 4; + static constexpr uint32_t CHANNELS = 24; + static constexpr uint32_t REGISTERS = 0x100; + static constexpr uint32_t ALL_CHANNELS = (1 << CHANNELS) - 1; + + // constructor + pcm_registers() { } + + // save/restore + void save_restore(ymfm_saved_state &state); + + // reset to initial state + void reset(); + + // update cache information + void cache_channel_data(uint32_t choffs, pcm_cache &cache); + + // direct read/write access + uint8_t read(uint32_t index ) { return m_regdata[index]; } + void write(uint32_t index, uint8_t data) { m_regdata[index] = data; } + + // system-wide registers + uint32_t memory_access_mode() const { return bitfield(m_regdata[0x02], 0); } + uint32_t memory_type() const { return bitfield(m_regdata[0x02], 1); } + uint32_t wave_table_header() const { return bitfield(m_regdata[0x02], 2, 3); } + uint32_t device_id() const { return bitfield(m_regdata[0x02], 5, 3); } + uint32_t memory_address() const { return (bitfield(m_regdata[0x03], 0, 6) << 16) | (m_regdata[0x04] << 8) | m_regdata[0x05]; } + uint32_t memory_data() const { return m_regdata[0x06]; } + uint32_t mix_fm_r() const { return bitfield(m_regdata[0xf8], 3, 3); } + uint32_t mix_fm_l() const { return bitfield(m_regdata[0xf8], 0, 3); } + uint32_t mix_pcm_r() const { return bitfield(m_regdata[0xf9], 3, 3); } + uint32_t mix_pcm_l() const { return bitfield(m_regdata[0xf9], 0, 3); } + + // per-channel registers + uint32_t ch_wave_table_num(uint32_t choffs) const { return m_regdata[choffs + 0x08] | (bitfield(m_regdata[choffs + 0x20], 0) << 8); } + uint32_t ch_fnumber(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x20], 1, 7) | (bitfield(m_regdata[choffs + 0x38], 0, 3) << 7); } + uint32_t ch_pseudo_reverb(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x38], 3); } + uint32_t ch_octave(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x38], 4, 4); } + uint32_t ch_total_level(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x50], 1, 7); } + uint32_t ch_level_direct(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x50], 0); } + uint32_t ch_keyon(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x68], 7); } + uint32_t ch_damp(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x68], 6); } + uint32_t ch_lfo_reset(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x68], 5); } + uint32_t ch_output_channel(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x68], 4); } + uint32_t ch_panpot(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x68], 0, 4); } + uint32_t ch_lfo_speed(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x80], 3, 3); } + uint32_t ch_vibrato(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x80], 0, 3); } + uint32_t ch_attack_rate(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x98], 4, 4); } + uint32_t ch_decay_rate(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0x98], 0, 4); } + uint32_t ch_sustain_level(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0xb0], 4, 4); } + uint32_t ch_sustain_rate(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0xb0], 0, 4); } + uint32_t ch_rate_correction(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0xc8], 4, 4); } + uint32_t ch_release_rate(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0xc8], 0, 4); } + uint32_t ch_am_depth(uint32_t choffs) const { return bitfield(m_regdata[choffs + 0xe0], 0, 3); } + + // return the memory address and increment it + uint32_t memory_address_autoinc() + { + uint32_t result = memory_address(); + uint32_t newval = result + 1; + m_regdata[0x05] = newval >> 0; + m_regdata[0x04] = newval >> 8; + m_regdata[0x03] = (newval >> 16) & 0x3f; + return result; + } + +private: + // internal helpers + uint32_t effective_rate(uint32_t raw, uint32_t correction); + + // internal state + uint8_t m_regdata[REGISTERS]; // register data +}; + + +// ======================> pcm_channel + +class pcm_channel +{ + static constexpr uint8_t KEY_ON = 0x01; + static constexpr uint8_t KEY_PENDING_ON = 0x02; + static constexpr uint8_t KEY_PENDING = 0x04; + + // "quiet" value, used to optimize when we can skip doing working + static constexpr uint32_t EG_QUIET = 0x200; + +public: + using output_data = ymfm_output; + + // constructor + pcm_channel(pcm_engine &owner, uint32_t choffs); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // reset the channel state + void reset(); + + // return the channel offset + uint32_t choffs() const { return m_choffs; } + + // prepare prior to clocking + bool prepare(); + + // master clocking function + void clock(uint32_t env_counter); + + // return the computed output value, with panning applied + void output(output_data &output) const; + + // signal key on/off + void keyonoff(bool on); + + // load a new wavetable entry + void load_wavetable(); + +private: + // internal helpers + void start_attack(); + void start_release(); + void clock_envelope(uint32_t env_counter); + int16_t fetch_sample() const; + uint8_t read_pcm(uint32_t address) const; + + // internal state + uint32_t const m_choffs; // channel offset + uint32_t m_baseaddr; // base address + uint32_t m_endpos; // ending position + uint32_t m_looppos; // loop position + uint32_t m_curpos; // current position + uint32_t m_nextpos; // next position + uint32_t m_lfo_counter; // LFO counter + envelope_state m_eg_state; // envelope state + uint16_t m_env_attenuation; // computed envelope attenuation + uint32_t m_total_level; // total level with as 7.10 for interp + uint8_t m_format; // sample format + uint8_t m_key_state; // current key state + pcm_cache m_cache; // cached data + pcm_registers &m_regs; // reference to registers + pcm_engine &m_owner; // reference to our owner +}; + + +// ======================> pcm_engine + +class pcm_engine +{ +public: + static constexpr int OUTPUTS = pcm_registers::OUTPUTS; + static constexpr int CHANNELS = pcm_registers::CHANNELS; + static constexpr uint32_t ALL_CHANNELS = pcm_registers::ALL_CHANNELS; + using output_data = pcm_channel::output_data; + + // constructor + pcm_engine(ymfm_interface &intf); + + // reset our status + void reset(); + + // save/restore + void save_restore(ymfm_saved_state &state); + + // master clocking function + void clock(uint32_t chanmask); + + // compute sum of channel outputs + void output(output_data &output, uint32_t chanmask); + + // read from the PCM registers + uint8_t read(uint32_t regnum); + + // write to the PCM registers + void write(uint32_t regnum, uint8_t data); + + // return a reference to our interface + ymfm_interface &intf() { return m_intf; } + + // return a reference to our registers + pcm_registers ®s() { return m_regs; } + +private: + // internal state + ymfm_interface &m_intf; // reference to the interface + uint32_t m_env_counter; // envelope counter + uint32_t m_modified_channels; // bitmask of modified channels + uint32_t m_active_channels; // bitmask of active channels + uint32_t m_prepare_count; // counter to do periodic prepare sweeps + std::unique_ptr m_channel[CHANNELS]; // array of channels + pcm_registers m_regs; // registers +}; + +} + +#endif // YMFM_PCM_H