mirror of
https://github.com/tildearrow/furnace.git
synced 2024-11-30 16:33:01 +00:00
427 lines
13 KiB
C
427 lines
13 KiB
C
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/*
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* Copyright (c) 2003, 2007-14 Matteo Frigo
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* Copyright (c) 2003, 2007-14 Massachusetts Institute of Technology
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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/* This file was automatically generated --- DO NOT EDIT */
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/* Generated on Tue Sep 14 10:45:29 EDT 2021 */
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#include "dft/codelet-dft.h"
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#if defined(ARCH_PREFERS_FMA) || defined(ISA_EXTENSION_PREFERS_FMA)
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/* Generated by: ../../../genfft/gen_twiddle_c.native -fma -simd -compact -variables 4 -pipeline-latency 8 -n 16 -name t1fv_16 -include dft/simd/t1f.h */
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/*
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* This function contains 87 FP additions, 64 FP multiplications,
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* (or, 53 additions, 30 multiplications, 34 fused multiply/add),
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* 36 stack variables, 3 constants, and 32 memory accesses
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*/
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#include "dft/simd/t1f.h"
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static void t1fv_16(R *ri, R *ii, const R *W, stride rs, INT mb, INT me, INT ms)
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{
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DVK(KP923879532, +0.923879532511286756128183189396788286822416626);
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DVK(KP707106781, +0.707106781186547524400844362104849039284835938);
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DVK(KP414213562, +0.414213562373095048801688724209698078569671875);
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{
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INT m;
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R *x;
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x = ri;
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for (m = mb, W = W + (mb * ((TWVL / VL) * 30)); m < me; m = m + VL, x = x + (VL * ms), W = W + (TWVL * 30), MAKE_VOLATILE_STRIDE(16, rs)) {
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V T4, TW, T9, T19, TD, TI, TZ, T1a, Tf, Tk, Tl, T13, T1c, Tq, Tv;
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V Tw, T16, T1d, T1, T3, T2;
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T1 = LD(&(x[0]), ms, &(x[0]));
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T2 = LD(&(x[WS(rs, 8)]), ms, &(x[0]));
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T3 = BYTWJ(&(W[TWVL * 14]), T2);
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T4 = VADD(T1, T3);
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TW = VSUB(T1, T3);
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{
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V T6, T8, T5, T7;
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T5 = LD(&(x[WS(rs, 4)]), ms, &(x[0]));
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T6 = BYTWJ(&(W[TWVL * 6]), T5);
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T7 = LD(&(x[WS(rs, 12)]), ms, &(x[0]));
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T8 = BYTWJ(&(W[TWVL * 22]), T7);
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T9 = VADD(T6, T8);
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T19 = VSUB(T6, T8);
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}
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{
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V TA, TH, TC, TF, TX, TY;
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{
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V Tz, TG, TB, TE;
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Tz = LD(&(x[WS(rs, 14)]), ms, &(x[0]));
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TA = BYTWJ(&(W[TWVL * 26]), Tz);
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TG = LD(&(x[WS(rs, 10)]), ms, &(x[0]));
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TH = BYTWJ(&(W[TWVL * 18]), TG);
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TB = LD(&(x[WS(rs, 6)]), ms, &(x[0]));
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TC = BYTWJ(&(W[TWVL * 10]), TB);
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TE = LD(&(x[WS(rs, 2)]), ms, &(x[0]));
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TF = BYTWJ(&(W[TWVL * 2]), TE);
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}
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TD = VADD(TA, TC);
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TI = VADD(TF, TH);
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TX = VSUB(TF, TH);
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TY = VSUB(TA, TC);
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TZ = VADD(TX, TY);
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T1a = VSUB(TY, TX);
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}
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{
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V Tc, Tj, Te, Th, T11, T12;
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{
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V Tb, Ti, Td, Tg;
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Tb = LD(&(x[WS(rs, 1)]), ms, &(x[WS(rs, 1)]));
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Tc = BYTWJ(&(W[0]), Tb);
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Ti = LD(&(x[WS(rs, 13)]), ms, &(x[WS(rs, 1)]));
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Tj = BYTWJ(&(W[TWVL * 24]), Ti);
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Td = LD(&(x[WS(rs, 9)]), ms, &(x[WS(rs, 1)]));
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Te = BYTWJ(&(W[TWVL * 16]), Td);
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Tg = LD(&(x[WS(rs, 5)]), ms, &(x[WS(rs, 1)]));
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Th = BYTWJ(&(W[TWVL * 8]), Tg);
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}
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Tf = VADD(Tc, Te);
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Tk = VADD(Th, Tj);
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Tl = VSUB(Tf, Tk);
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T11 = VSUB(Tc, Te);
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T12 = VSUB(Th, Tj);
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T13 = VFNMS(LDK(KP414213562), T12, T11);
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T1c = VFMA(LDK(KP414213562), T11, T12);
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}
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{
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V Tn, Tu, Tp, Ts, T14, T15;
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{
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V Tm, Tt, To, Tr;
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Tm = LD(&(x[WS(rs, 15)]), ms, &(x[WS(rs, 1)]));
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Tn = BYTWJ(&(W[TWVL * 28]), Tm);
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Tt = LD(&(x[WS(rs, 11)]), ms, &(x[WS(rs, 1)]));
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Tu = BYTWJ(&(W[TWVL * 20]), Tt);
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To = LD(&(x[WS(rs, 7)]), ms, &(x[WS(rs, 1)]));
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Tp = BYTWJ(&(W[TWVL * 12]), To);
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Tr = LD(&(x[WS(rs, 3)]), ms, &(x[WS(rs, 1)]));
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Ts = BYTWJ(&(W[TWVL * 4]), Tr);
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}
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Tq = VADD(Tn, Tp);
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Tv = VADD(Ts, Tu);
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Tw = VSUB(Tq, Tv);
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T14 = VSUB(Tn, Tp);
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T15 = VSUB(Tu, Ts);
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T16 = VFNMS(LDK(KP414213562), T15, T14);
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T1d = VFMA(LDK(KP414213562), T14, T15);
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}
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{
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V Ty, TM, TL, TN;
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{
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V Ta, Tx, TJ, TK;
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Ta = VSUB(T4, T9);
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Tx = VADD(Tl, Tw);
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Ty = VFNMS(LDK(KP707106781), Tx, Ta);
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TM = VFMA(LDK(KP707106781), Tx, Ta);
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TJ = VSUB(TD, TI);
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TK = VSUB(Tw, Tl);
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TL = VFNMS(LDK(KP707106781), TK, TJ);
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TN = VFMA(LDK(KP707106781), TK, TJ);
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}
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ST(&(x[WS(rs, 6)]), VFNMSI(TL, Ty), ms, &(x[0]));
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ST(&(x[WS(rs, 2)]), VFMAI(TN, TM), ms, &(x[0]));
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ST(&(x[WS(rs, 10)]), VFMAI(TL, Ty), ms, &(x[0]));
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ST(&(x[WS(rs, 14)]), VFNMSI(TN, TM), ms, &(x[0]));
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}
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{
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V T1k, T1o, T1n, T1p;
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{
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V T1i, T1j, T1l, T1m;
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T1i = VFNMS(LDK(KP707106781), TZ, TW);
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T1j = VADD(T1c, T1d);
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T1k = VFNMS(LDK(KP923879532), T1j, T1i);
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T1o = VFMA(LDK(KP923879532), T1j, T1i);
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T1l = VFMA(LDK(KP707106781), T1a, T19);
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T1m = VSUB(T16, T13);
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T1n = VFNMS(LDK(KP923879532), T1m, T1l);
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T1p = VFMA(LDK(KP923879532), T1m, T1l);
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}
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ST(&(x[WS(rs, 5)]), VFNMSI(T1n, T1k), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 13)]), VFNMSI(T1p, T1o), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 11)]), VFMAI(T1n, T1k), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 3)]), VFMAI(T1p, T1o), ms, &(x[WS(rs, 1)]));
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}
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{
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V TQ, TU, TT, TV;
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{
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V TO, TP, TR, TS;
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TO = VADD(T4, T9);
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TP = VADD(TI, TD);
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TQ = VADD(TO, TP);
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TU = VSUB(TO, TP);
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TR = VADD(Tf, Tk);
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TS = VADD(Tq, Tv);
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TT = VADD(TR, TS);
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TV = VSUB(TS, TR);
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}
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ST(&(x[WS(rs, 8)]), VSUB(TQ, TT), ms, &(x[0]));
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ST(&(x[WS(rs, 4)]), VFMAI(TV, TU), ms, &(x[0]));
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ST(&(x[0]), VADD(TQ, TT), ms, &(x[0]));
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ST(&(x[WS(rs, 12)]), VFNMSI(TV, TU), ms, &(x[0]));
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}
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{
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V T18, T1g, T1f, T1h;
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{
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V T10, T17, T1b, T1e;
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T10 = VFMA(LDK(KP707106781), TZ, TW);
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T17 = VADD(T13, T16);
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T18 = VFNMS(LDK(KP923879532), T17, T10);
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T1g = VFMA(LDK(KP923879532), T17, T10);
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T1b = VFNMS(LDK(KP707106781), T1a, T19);
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T1e = VSUB(T1c, T1d);
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T1f = VFNMS(LDK(KP923879532), T1e, T1b);
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T1h = VFMA(LDK(KP923879532), T1e, T1b);
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}
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ST(&(x[WS(rs, 9)]), VFNMSI(T1f, T18), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 15)]), VFMAI(T1h, T1g), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 7)]), VFMAI(T1f, T18), ms, &(x[WS(rs, 1)]));
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ST(&(x[WS(rs, 1)]), VFNMSI(T1h, T1g), ms, &(x[WS(rs, 1)]));
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}
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}
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}
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VLEAVE();
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}
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static const tw_instr twinstr[] = {
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VTW(0, 1),
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VTW(0, 2),
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VTW(0, 3),
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VTW(0, 4),
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VTW(0, 5),
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VTW(0, 6),
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VTW(0, 7),
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VTW(0, 8),
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VTW(0, 9),
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VTW(0, 10),
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VTW(0, 11),
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VTW(0, 12),
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VTW(0, 13),
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VTW(0, 14),
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VTW(0, 15),
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{ TW_NEXT, VL, 0 }
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};
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static const ct_desc desc = { 16, XSIMD_STRING("t1fv_16"), twinstr, &GENUS, { 53, 30, 34, 0 }, 0, 0, 0 };
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void XSIMD(codelet_t1fv_16) (planner *p) {
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X(kdft_dit_register) (p, t1fv_16, &desc);
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}
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#else
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/* Generated by: ../../../genfft/gen_twiddle_c.native -simd -compact -variables 4 -pipeline-latency 8 -n 16 -name t1fv_16 -include dft/simd/t1f.h */
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/*
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* This function contains 87 FP additions, 42 FP multiplications,
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* (or, 83 additions, 38 multiplications, 4 fused multiply/add),
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* 36 stack variables, 3 constants, and 32 memory accesses
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*/
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#include "dft/simd/t1f.h"
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static void t1fv_16(R *ri, R *ii, const R *W, stride rs, INT mb, INT me, INT ms)
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{
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DVK(KP923879532, +0.923879532511286756128183189396788286822416626);
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DVK(KP382683432, +0.382683432365089771728459984030398866761344562);
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DVK(KP707106781, +0.707106781186547524400844362104849039284835938);
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{
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INT m;
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R *x;
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x = ri;
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for (m = mb, W = W + (mb * ((TWVL / VL) * 30)); m < me; m = m + VL, x = x + (VL * ms), W = W + (TWVL * 30), MAKE_VOLATILE_STRIDE(16, rs)) {
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V TJ, T10, TD, T11, T1b, T1c, Ty, TK, T16, T17, T18, Tb, TN, T13, T14;
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V T15, Tm, TM, TG, TI, TH;
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TG = LD(&(x[0]), ms, &(x[0]));
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TH = LD(&(x[WS(rs, 8)]), ms, &(x[0]));
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TI = BYTWJ(&(W[TWVL * 14]), TH);
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TJ = VSUB(TG, TI);
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T10 = VADD(TG, TI);
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{
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V TA, TC, Tz, TB;
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Tz = LD(&(x[WS(rs, 4)]), ms, &(x[0]));
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TA = BYTWJ(&(W[TWVL * 6]), Tz);
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TB = LD(&(x[WS(rs, 12)]), ms, &(x[0]));
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TC = BYTWJ(&(W[TWVL * 22]), TB);
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TD = VSUB(TA, TC);
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T11 = VADD(TA, TC);
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}
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{
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V Tp, Tw, Tr, Tu, Ts, Tx;
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{
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V To, Tv, Tq, Tt;
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To = LD(&(x[WS(rs, 14)]), ms, &(x[0]));
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Tp = BYTWJ(&(W[TWVL * 26]), To);
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Tv = LD(&(x[WS(rs, 10)]), ms, &(x[0]));
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Tw = BYTWJ(&(W[TWVL * 18]), Tv);
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Tq = LD(&(x[WS(rs, 6)]), ms, &(x[0]));
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Tr = BYTWJ(&(W[TWVL * 10]), Tq);
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Tt = LD(&(x[WS(rs, 2)]), ms, &(x[0]));
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Tu = BYTWJ(&(W[TWVL * 2]), Tt);
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}
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T1b = VADD(Tp, Tr);
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T1c = VADD(Tu, Tw);
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Ts = VSUB(Tp, Tr);
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Tx = VSUB(Tu, Tw);
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Ty = VMUL(LDK(KP707106781), VSUB(Ts, Tx));
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TK = VMUL(LDK(KP707106781), VADD(Tx, Ts));
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}
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{
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V T2, T9, T4, T7, T5, Ta;
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{
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V T1, T8, T3, T6;
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T1 = LD(&(x[WS(rs, 15)]), ms, &(x[WS(rs, 1)]));
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T2 = BYTWJ(&(W[TWVL * 28]), T1);
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T8 = LD(&(x[WS(rs, 11)]), ms, &(x[WS(rs, 1)]));
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T9 = BYTWJ(&(W[TWVL * 20]), T8);
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T3 = LD(&(x[WS(rs, 7)]), ms, &(x[WS(rs, 1)]));
|
||
|
|
T4 = BYTWJ(&(W[TWVL * 12]), T3);
|
||
|
|
T6 = LD(&(x[WS(rs, 3)]), ms, &(x[WS(rs, 1)]));
|
||
|
|
T7 = BYTWJ(&(W[TWVL * 4]), T6);
|
||
|
|
}
|
||
|
|
T16 = VADD(T2, T4);
|
||
|
|
T17 = VADD(T7, T9);
|
||
|
|
T18 = VSUB(T16, T17);
|
||
|
|
T5 = VSUB(T2, T4);
|
||
|
|
Ta = VSUB(T7, T9);
|
||
|
|
Tb = VFNMS(LDK(KP923879532), Ta, VMUL(LDK(KP382683432), T5));
|
||
|
|
TN = VFMA(LDK(KP923879532), T5, VMUL(LDK(KP382683432), Ta));
|
||
|
|
}
|
||
|
|
{
|
||
|
|
V Td, Tk, Tf, Ti, Tg, Tl;
|
||
|
|
{
|
||
|
|
V Tc, Tj, Te, Th;
|
||
|
|
Tc = LD(&(x[WS(rs, 1)]), ms, &(x[WS(rs, 1)]));
|
||
|
|
Td = BYTWJ(&(W[0]), Tc);
|
||
|
|
Tj = LD(&(x[WS(rs, 13)]), ms, &(x[WS(rs, 1)]));
|
||
|
|
Tk = BYTWJ(&(W[TWVL * 24]), Tj);
|
||
|
|
Te = LD(&(x[WS(rs, 9)]), ms, &(x[WS(rs, 1)]));
|
||
|
|
Tf = BYTWJ(&(W[TWVL * 16]), Te);
|
||
|
|
Th = LD(&(x[WS(rs, 5)]), ms, &(x[WS(rs, 1)]));
|
||
|
|
Ti = BYTWJ(&(W[TWVL * 8]), Th);
|
||
|
|
}
|
||
|
|
T13 = VADD(Td, Tf);
|
||
|
|
T14 = VADD(Ti, Tk);
|
||
|
|
T15 = VSUB(T13, T14);
|
||
|
|
Tg = VSUB(Td, Tf);
|
||
|
|
Tl = VSUB(Ti, Tk);
|
||
|
|
Tm = VFMA(LDK(KP382683432), Tg, VMUL(LDK(KP923879532), Tl));
|
||
|
|
TM = VFNMS(LDK(KP382683432), Tl, VMUL(LDK(KP923879532), Tg));
|
||
|
|
}
|
||
|
|
{
|
||
|
|
V T1a, T1g, T1f, T1h;
|
||
|
|
{
|
||
|
|
V T12, T19, T1d, T1e;
|
||
|
|
T12 = VSUB(T10, T11);
|
||
|
|
T19 = VMUL(LDK(KP707106781), VADD(T15, T18));
|
||
|
|
T1a = VADD(T12, T19);
|
||
|
|
T1g = VSUB(T12, T19);
|
||
|
|
T1d = VSUB(T1b, T1c);
|
||
|
|
T1e = VMUL(LDK(KP707106781), VSUB(T18, T15));
|
||
|
|
T1f = VBYI(VADD(T1d, T1e));
|
||
|
|
T1h = VBYI(VSUB(T1e, T1d));
|
||
|
|
}
|
||
|
|
ST(&(x[WS(rs, 14)]), VSUB(T1a, T1f), ms, &(x[0]));
|
||
|
|
ST(&(x[WS(rs, 6)]), VADD(T1g, T1h), ms, &(x[0]));
|
||
|
|
ST(&(x[WS(rs, 2)]), VADD(T1a, T1f), ms, &(x[0]));
|
||
|
|
ST(&(x[WS(rs, 10)]), VSUB(T1g, T1h), ms, &(x[0]));
|
||
|
|
}
|
||
|
|
{
|
||
|
|
V T1k, T1o, T1n, T1p;
|
||
|
|
{
|
||
|
|
V T1i, T1j, T1l, T1m;
|
||
|
|
T1i = VADD(T10, T11);
|
||
|
|
T1j = VADD(T1c, T1b);
|
||
|
|
T1k = VADD(T1i, T1j);
|
||
|
|
T1o = VSUB(T1i, T1j);
|
||
|
|
T1l = VADD(T13, T14);
|
||
|
|
T1m = VADD(T16, T17);
|
||
|
|
T1n = VADD(T1l, T1m);
|
||
|
|
T1p = VBYI(VSUB(T1m, T1l));
|
||
|
|
}
|
||
|
|
ST(&(x[WS(rs, 8)]), VSUB(T1k, T1n), ms, &(x[0]));
|
||
|
|
ST(&(x[WS(rs, 4)]), VADD(T1o, T1p), ms, &(x[0]));
|
||
|
|
ST(&(x[0]), VADD(T1k, T1n), ms, &(x[0]));
|
||
|
|
ST(&(x[WS(rs, 12)]), VSUB(T1o, T1p), ms, &(x[0]));
|
||
|
|
}
|
||
|
|
{
|
||
|
|
V TF, TQ, TP, TR;
|
||
|
|
{
|
||
|
|
V Tn, TE, TL, TO;
|
||
|
|
Tn = VSUB(Tb, Tm);
|
||
|
|
TE = VSUB(Ty, TD);
|
||
|
|
TF = VBYI(VSUB(Tn, TE));
|
||
|
|
TQ = VBYI(VADD(TE, Tn));
|
||
|
|
TL = VADD(TJ, TK);
|
||
|
|
TO = VADD(TM, TN);
|
||
|
|
TP = VSUB(TL, TO);
|
||
|
|
TR = VADD(TL, TO);
|
||
|
|
}
|
||
|
|
ST(&(x[WS(rs, 7)]), VADD(TF, TP), ms, &(x[WS(rs, 1)]));
|
||
|
|
ST(&(x[WS(rs, 15)]), VSUB(TR, TQ), ms, &(x[WS(rs, 1)]));
|
||
|
|
ST(&(x[WS(rs, 9)]), VSUB(TP, TF), ms, &(x[WS(rs, 1)]));
|
||
|
|
ST(&(x[WS(rs, 1)]), VADD(TQ, TR), ms, &(x[WS(rs, 1)]));
|
||
|
|
}
|
||
|
|
{
|
||
|
|
V TU, TY, TX, TZ;
|
||
|
|
{
|
||
|
|
V TS, TT, TV, TW;
|
||
|
|
TS = VSUB(TJ, TK);
|
||
|
|
TT = VADD(Tm, Tb);
|
||
|
|
TU = VADD(TS, TT);
|
||
|
|
TY = VSUB(TS, TT);
|
||
|
|
TV = VADD(TD, Ty);
|
||
|
|
TW = VSUB(TN, TM);
|
||
|
|
TX = VBYI(VADD(TV, TW));
|
||
|
|
TZ = VBYI(VSUB(TW, TV));
|
||
|
|
}
|
||
|
|
ST(&(x[WS(rs, 13)]), VSUB(TU, TX), ms, &(x[WS(rs, 1)]));
|
||
|
|
ST(&(x[WS(rs, 5)]), VADD(TY, TZ), ms, &(x[WS(rs, 1)]));
|
||
|
|
ST(&(x[WS(rs, 3)]), VADD(TU, TX), ms, &(x[WS(rs, 1)]));
|
||
|
|
ST(&(x[WS(rs, 11)]), VSUB(TY, TZ), ms, &(x[WS(rs, 1)]));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
VLEAVE();
|
||
|
|
}
|
||
|
|
|
||
|
|
static const tw_instr twinstr[] = {
|
||
|
|
VTW(0, 1),
|
||
|
|
VTW(0, 2),
|
||
|
|
VTW(0, 3),
|
||
|
|
VTW(0, 4),
|
||
|
|
VTW(0, 5),
|
||
|
|
VTW(0, 6),
|
||
|
|
VTW(0, 7),
|
||
|
|
VTW(0, 8),
|
||
|
|
VTW(0, 9),
|
||
|
|
VTW(0, 10),
|
||
|
|
VTW(0, 11),
|
||
|
|
VTW(0, 12),
|
||
|
|
VTW(0, 13),
|
||
|
|
VTW(0, 14),
|
||
|
|
VTW(0, 15),
|
||
|
|
{ TW_NEXT, VL, 0 }
|
||
|
|
};
|
||
|
|
|
||
|
|
static const ct_desc desc = { 16, XSIMD_STRING("t1fv_16"), twinstr, &GENUS, { 83, 38, 4, 0 }, 0, 0, 0 };
|
||
|
|
|
||
|
|
void XSIMD(codelet_t1fv_16) (planner *p) {
|
||
|
|
X(kdft_dit_register) (p, t1fv_16, &desc);
|
||
|
|
}
|
||
|
|
#endif
|